riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

clean up D$ store data unit

Browse Source
This commit is contained in:
Andrew Waterman 2012-03-01 18:49:00 -08:00
parent de73eef409
commit 4c3f7a36ce
1 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
uncore/coherence.scala
View File

@ -90,8 +90,8 @@ class ioTileLink extends Bundle {
val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
} }
trait CoherencePolicy { object cpuCmdToRW {
def cpuCmdToRW( cmd: Bits): (Bool, Bool) = { def apply(cmd: Bits): (Bool, Bool) = {
val store = (cmd === M_XWR) val store = (cmd === M_XWR)
val load = (cmd === M_XRD) val load = (cmd === M_XRD)
val amo = cmd(3).toBool val amo = cmd(3).toBool
@ -101,6 +101,9 @@ trait CoherencePolicy {
} }
} }
trait CoherencePolicy {
}
trait ThreeStateIncoherence extends CoherencePolicy { trait ThreeStateIncoherence extends CoherencePolicy {
val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() } val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }