riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

unit tests in Coreplex instead of Tile

Browse Source
This commit is contained in:
Howard Mao 2016-08-10 11:26:14 -07:00
parent 571d579b86
commit 4bfa7ceb6a
2 changed files with 11 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/main/scala/TestConfigs.scala
View File

@ -168,23 +168,14 @@ class WithNastiConverterTest extends Config(
class WithUnitTest extends Config( class WithUnitTest extends Config(
(pname, site, here) => pname match { (pname, site, here) => pname match {
case BuildTiles => { case BuildCoreplex => {
val groundtest = if (site(XLen) == 64) val groundtest = if (site(XLen) == 64)
DefaultTestSuites.groundtest64 DefaultTestSuites.groundtest64
else else
DefaultTestSuites.groundtest32 DefaultTestSuites.groundtest32
TestGeneration.addSuite(groundtest("p")) TestGeneration.addSuite(groundtest("p"))
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks) TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
(0 until site(NTiles)).map { i => (p: Parameters) => Module(new UnitTestCoreplex(p))
(r: Bool, p: Parameters) => {
Module(new UnitTestTile(resetSignal = r)(p.alterPartial({
case TLId => "L1toL2"
case NCachedTileLinkPorts => 0
case NUncachedTileLinkPorts => 0
case RoccNCSRs => 0
})))
}
}
} }
case UnitTests => (testParams: Parameters) => case UnitTests => (testParams: Parameters) =>
JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams) JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)

14
src/main/scala/UnitTest.scala
View File

@ -3,14 +3,18 @@ package rocketchip
import Chisel._ import Chisel._
import junctions.unittests.UnitTestSuite import junctions.unittests.UnitTestSuite
import rocket.Tile import rocket.Tile
import uncore.tilelink.TLId
import cde.Parameters import cde.Parameters
class UnitTestTile(clockSignal: Clock = null, resetSignal: Bool = null) class UnitTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
(implicit p: Parameters) extends Tile(clockSignal, resetSignal)(p) { require(!exportMMIO)
require(!exportBus)
require(nMemChannels == 0)
require(io.cached.size == 0) io.debug.req.ready := Bool(false)
require(io.uncached.size == 0) io.debug.resp.valid := Bool(false)
val tests = Module(new UnitTestSuite) val l1params = p.alterPartial({ case TLId => "L1toL2" })
val tests = Module(new UnitTestSuite()(l1params))
when (tests.io.finished) { stop() } when (tests.io.finished) { stop() }
} }