diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala index 4a2d28b7..3d4ccac2 100644 --- a/src/main/scala/TestConfigs.scala +++ b/src/main/scala/TestConfigs.scala @@ -168,23 +168,14 @@ class WithNastiConverterTest extends Config( class WithUnitTest extends Config( (pname, site, here) => pname match { - case BuildTiles => { + case BuildCoreplex => { val groundtest = if (site(XLen) == 64) DefaultTestSuites.groundtest64 else DefaultTestSuites.groundtest32 TestGeneration.addSuite(groundtest("p")) TestGeneration.addSuite(DefaultTestSuites.emptyBmarks) - (0 until site(NTiles)).map { i => - (r: Bool, p: Parameters) => { - Module(new UnitTestTile(resetSignal = r)(p.alterPartial({ - case TLId => "L1toL2" - case NCachedTileLinkPorts => 0 - case NUncachedTileLinkPorts => 0 - case RoccNCSRs => 0 - }))) - } - } + (p: Parameters) => Module(new UnitTestCoreplex(p)) } case UnitTests => (testParams: Parameters) => JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams) diff --git a/src/main/scala/UnitTest.scala b/src/main/scala/UnitTest.scala index f9d76c93..e31110cb 100644 --- a/src/main/scala/UnitTest.scala +++ b/src/main/scala/UnitTest.scala @@ -3,14 +3,18 @@ package rocketchip import Chisel._ import junctions.unittests.UnitTestSuite import rocket.Tile +import uncore.tilelink.TLId import cde.Parameters -class UnitTestTile(clockSignal: Clock = null, resetSignal: Bool = null) - (implicit p: Parameters) extends Tile(clockSignal, resetSignal)(p) { +class UnitTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) { + require(!exportMMIO) + require(!exportBus) + require(nMemChannels == 0) - require(io.cached.size == 0) - require(io.uncached.size == 0) + io.debug.req.ready := Bool(false) + io.debug.resp.valid := Bool(false) - val tests = Module(new UnitTestSuite) + val l1params = p.alterPartial({ case TLId => "L1toL2" }) + val tests = Module(new UnitTestSuite()(l1params)) when (tests.io.finished) { stop() } }