riscv/rocket-chip
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Remove JTAG vpi from VCS build

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h/t @mwachs5

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
This commit is contained in:
Schuyler Eldridge 2018-02-26 15:12:18 -05:00
parent d0e350976a
commit 4bcc42550e
1 changed files with 1 additions and 4 deletions
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5
vsim/Makefrag
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@ -5,7 +5,6 @@
# Verilog sources # Verilog sources
bb_vsrcs = \ bb_vsrcs = \
$(base_dir)/vsrc/jtag_vpi.v \
$(base_dir)/vsrc/plusarg_reader.v \ $(base_dir)/vsrc/plusarg_reader.v \
$(base_dir)/vsrc/ClockDivider2.v \ $(base_dir)/vsrc/ClockDivider2.v \
$(base_dir)/vsrc/ClockDivider3.v \ $(base_dir)/vsrc/ClockDivider3.v \
@ -24,8 +23,7 @@ sim_vsrcs = \
sim_csrcs = \ sim_csrcs = \
$(base_dir)/csrc/SimDTM.cc \ $(base_dir)/csrc/SimDTM.cc \
$(base_dir)/csrc/SimJTAG.cc \ $(base_dir)/csrc/SimJTAG.cc \
$(base_dir)/csrc/remote_bitbang.cc \ $(base_dir)/csrc/remote_bitbang.cc
$(base_dir)/csrc/jtag_vpi.c
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# Build Verilog # Build Verilog
@ -60,7 +58,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
+libext+.v \ +libext+.v \
VCS_OPTS += +vpi VCS_OPTS += +vpi
VCS_OPTS += -P $(base_dir)/vsrc/jtag_vpi.tab
VCS_OPTS += -CC "-DVCS_VPI" VCS_OPTS += -CC "-DVCS_VPI"