riscv/rocket-chip
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rocketchip: add a parameter-controlled debug port

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This commit is contained in:
Wesley W. Terpstra 2016-11-23 15:35:53 -08:00
parent 76fa62a928
commit 4b9dc78951
1 changed files with 36 additions and 0 deletions
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36
src/main/scala/rocketchip/RISCVPlatform.scala
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@ -11,6 +11,8 @@ import util._
import junctions.JTAGIO import junctions.JTAGIO
import coreplex._ import coreplex._
/// Core with JTAG for debug only
trait PeripheryJTAG extends TopNetwork { trait PeripheryJTAG extends TopNetwork {
val module: PeripheryJTAGModule val module: PeripheryJTAGModule
val coreplex: CoreplexRISCVPlatform val coreplex: CoreplexRISCVPlatform
@ -34,6 +36,8 @@ trait PeripheryJTAGModule extends TopNetworkModule {
dtm.reset := io.jtag.TRST dtm.reset := io.jtag.TRST
} }
/// Core with DTM for debug only
trait PeripheryDTM extends TopNetwork { trait PeripheryDTM extends TopNetwork {
val module: PeripheryDTMModule val module: PeripheryDTMModule
val coreplex: CoreplexRISCVPlatform val coreplex: CoreplexRISCVPlatform
@ -52,6 +56,36 @@ trait PeripheryDTMModule extends TopNetworkModule {
outer.coreplex.module.io.debug <> ToAsyncDebugBus(io.debug) outer.coreplex.module.io.debug <> ToAsyncDebugBus(io.debug)
} }
/// Core with DTM or JTAG based on a parameter
trait PeripheryDebug extends TopNetwork {
val module: PeripheryDebugModule
val coreplex: CoreplexRISCVPlatform
}
trait PeripheryDebugBundle extends TopNetworkBundle {
val outer: PeripheryDebug
val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO().flip)
val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(true).flip)
}
trait PeripheryDebugModule extends TopNetworkModule {
val outer: PeripheryDebug
val io: PeripheryDebugBundle
io.debug.foreach { dbg => outer.coreplex.module.io.debug <> ToAsyncDebugBus(dbg) }
io.jtag.foreach { jtag =>
val dtm = Module (new JtagDTMWithSync)
dtm.clock := jtag.TCK
dtm.reset := jtag.TRST
dtm.io.jtag <> jtag
outer.coreplex.module.io.debug <> dtm.io.debug
}
}
/// Real-time clock is based on RTCPeriod relative to Top clock
trait PeripheryCounter extends TopNetwork { trait PeripheryCounter extends TopNetwork {
val module: PeripheryCounterModule val module: PeripheryCounterModule
val coreplex: CoreplexRISCVPlatform val coreplex: CoreplexRISCVPlatform
@ -75,6 +109,8 @@ trait PeripheryCounterModule extends TopNetworkModule {
} }
} }
/// Coreplex will power-on running at 0x1000 (BootROM)
trait HardwiredResetVector extends TopNetwork { trait HardwiredResetVector extends TopNetwork {
val module: HardwiredResetVectorModule val module: HardwiredResetVectorModule
val coreplex: CoreplexRISCVPlatform val coreplex: CoreplexRISCVPlatform