riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: mask out unnecessary address bits

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-08-26 14:13:09 -07:00
parent e24ba61754
commit 4b99bd3be1
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
uncore/src/main/scala/tilelink2/Bases.scala
View File

@ -31,6 +31,10 @@ abstract class TLFactory
bindings.foreach { case (x, i, y, j, s) => bindings.foreach { case (x, i, y, j, s) =>
TLMonitor.legalize(y.bundleOut(j), y.edgesOut(j), x.bundleIn(i), x.edgesIn(i), s) TLMonitor.legalize(y.bundleOut(j), y.edgesOut(j), x.bundleIn(i), x.edgesIn(i), s)
x.bundleIn(i).<>(y.bundleOut(j))(s) x.bundleIn(i).<>(y.bundleOut(j))(s)
val mask = ~UInt(x.edgesIn(i).manager.beatBytes - 1)
x.bundleIn (i).a.bits.address.:=(mask & y.bundleOut(j).a.bits.address)(s)
y.bundleOut(j).b.bits.address.:=(mask & x.bundleIn (i).b.bits.address)(s)
x.bundleIn (i).c.bits.address.:=(mask & y.bundleOut(j).c.bits.address)(s)
} }
} }
} }