AsyncCrossing: disambiguate the file name
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@ -137,7 +137,7 @@ class TLAsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) ext
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/** Synthesizeable unit tests */
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/** Synthesizeable unit tests */
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import unittest._
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import unittest._
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class TLRAMCrossing(implicit p: Parameters) extends LazyModule {
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class TLRAMAsyncCrossing(implicit p: Parameters) extends LazyModule {
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val model = LazyModule(new TLRAMModel)
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val model = LazyModule(new TLRAMModel)
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val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
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val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
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val fuzz = LazyModule(new TLFuzzer(5000))
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val fuzz = LazyModule(new TLFuzzer(5000))
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@ -168,6 +168,6 @@ class TLRAMCrossing(implicit p: Parameters) extends LazyModule {
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}
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}
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}
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}
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class TLRAMCrossingTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
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class TLRAMAsyncCrossingTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
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io.finished := Module(LazyModule(new TLRAMCrossing).module).io.finished
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io.finished := Module(LazyModule(new TLRAMAsyncCrossing).module).io.finished
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}
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}
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@ -30,7 +30,7 @@ class WithTLSimpleUnitTests extends Config((site, here, up) => {
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Module(new uncore.tilelink2.TLRAMSimpleTest(16)),
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Module(new uncore.tilelink2.TLRAMSimpleTest(16)),
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Module(new uncore.tilelink2.TLRR0Test),
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Module(new uncore.tilelink2.TLRR0Test),
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Module(new uncore.tilelink2.TLRR1Test),
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Module(new uncore.tilelink2.TLRR1Test),
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Module(new uncore.tilelink2.TLRAMCrossingTest) ) }
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Module(new uncore.tilelink2.TLRAMAsyncCrossingTest) ) }
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})
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})
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class WithTLWidthUnitTests extends Config((site, here, up) => {
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class WithTLWidthUnitTests extends Config((site, here, up) => {
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