riscv/rocket-chip
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Merge pull request #911 from freechipsproject/fix-dcache-bug

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Fix D$ ready-valid signaling bug
This commit is contained in:
Yunsup Lee 2017-07-31 19:14:16 -07:00 committed by GitHub
commit 4b33249812
2 changed files with 10 additions and 7 deletions
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15
src/main/scala/rocket/DCache.scala
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@ -430,11 +430,19 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
} }
} }
// Finish TileLink transaction by issuing a GrantAck
tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant
tl_out.e.bits := edge.GrantAck(tl_out.d.bits)
assert(tl_out.e.fire() === (tl_out.d.fire() && d_first && grantIsCached))
// data refill // data refill
// note this ready-valid signaling ignores E-channel backpressure, which // note this ready-valid signaling ignores E-channel backpressure, which
// benignly means the data RAM might occasionally be redundantly written // benignly means the data RAM might occasionally be redundantly written
dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant
when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.d.ready := false } when (grantIsRefill && !dataArb.io.in(1).ready) {
tl_out.e.valid := false
tl_out.d.ready := false
}
dataArb.io.in(1).bits.write := true dataArb.io.in(1).bits.write := true
dataArb.io.in(1).bits.addr := s2_req_block_addr | d_address_inc dataArb.io.in(1).bits.addr := s2_req_block_addr | d_address_inc
dataArb.io.in(1).bits.way_en := s2_victim_way dataArb.io.in(1).bits.way_en := s2_victim_way
@ -463,11 +471,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
} }
} }
// Finish TileLink transaction by issuing a GrantAck
tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant
tl_out.e.bits := edge.GrantAck(tl_out.d.bits)
when (tl_out.e.fire()) { assert(tl_out.d.fire()) }
// Handle an incoming TileLink Probe message // Handle an incoming TileLink Probe message
val block_probe = releaseInFlight || grantInProgress || blockProbeAfterGrantCount > 0 || lrscValid || (s2_valid_hit && s2_lr) val block_probe = releaseInFlight || grantInProgress || blockProbeAfterGrantCount > 0 || lrscValid || (s2_valid_hit && s2_lr)
metaArb.io.in(6).valid := tl_out.b.valid && !block_probe metaArb.io.in(6).valid := tl_out.b.valid && !block_probe

2
src/main/scala/tile/RocketTile.scala
View File

@ -177,7 +177,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
def optionalMasterBuffer(in: TLOutwardNode): TLOutwardNode = { def optionalMasterBuffer(in: TLOutwardNode): TLOutwardNode = {
if (rtp.boundaryBuffers) { if (rtp.boundaryBuffers) {
val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams.default)) val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
mbuf.node :=* in mbuf.node :=* in
mbuf.node mbuf.node
} else { } else {