From 5681693ccc6ef8d8bc14177352acd1b39dc98959 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 31 Jul 2017 18:05:14 -0700
Subject: [PATCH 1/2] Fix a D$ ready-valid signaling regression

I broke this in 66d06460fab4110b886fa7626697cbf39ace8cfd.
---
 src/main/scala/rocket/DCache.scala | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
index a53121c1..223fade9 100644
--- a/src/main/scala/rocket/DCache.scala
+++ b/src/main/scala/rocket/DCache.scala
@@ -430,11 +430,19 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
     }
   }
 
+  // Finish TileLink transaction by issuing a GrantAck
+  tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant
+  tl_out.e.bits := edge.GrantAck(tl_out.d.bits)
+  assert(tl_out.e.fire() === (tl_out.d.fire() && d_first && grantIsCached))
+
   // data refill
   // note this ready-valid signaling ignores E-channel backpressure, which
   // benignly means the data RAM might occasionally be redundantly written
   dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant
-  when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.d.ready := false }
+  when (grantIsRefill && !dataArb.io.in(1).ready) {
+    tl_out.e.valid := false
+    tl_out.d.ready := false
+  }
   dataArb.io.in(1).bits.write := true
   dataArb.io.in(1).bits.addr :=  s2_req_block_addr | d_address_inc
   dataArb.io.in(1).bits.way_en := s2_victim_way
@@ -463,11 +471,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
     }
   }
 
-  // Finish TileLink transaction by issuing a GrantAck
-  tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant
-  tl_out.e.bits := edge.GrantAck(tl_out.d.bits)
-  when (tl_out.e.fire()) { assert(tl_out.d.fire()) }
-
   // Handle an incoming TileLink Probe message
   val block_probe = releaseInFlight || grantInProgress || blockProbeAfterGrantCount > 0 || lrscValid || (s2_valid_hit && s2_lr)
   metaArb.io.in(6).valid := tl_out.b.valid && !block_probe

From e140893a0171da69bddabeee6749a03632a76bd9 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 31 Jul 2017 18:06:54 -0700
Subject: [PATCH 2/2] Use 1-entry queue on processor-side E-channel

The cache can't sink a grant every cycle, so extra E buffering doesn't help.
---
 src/main/scala/tile/RocketTile.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index 7323a30b..60b50738 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -177,7 +177,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
 
   def optionalMasterBuffer(in: TLOutwardNode): TLOutwardNode = {
     if (rtp.boundaryBuffers) {
-      val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams.default))
+      val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
       mbuf.node :=* in
       mbuf.node
     } else {