fixes to get groundtest working with priv-1.9 changes
This commit is contained in:
parent
c7c8ae5468
commit
487d0b356e
11
csrc/mm.cc
11
csrc/mm.cc
@ -10,11 +10,7 @@
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void mm_t::write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size)
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void mm_t::write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size)
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{
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{
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strb &= ((1 << size) - 1) << (addr % word_size);
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strb &= ((1 << size) - 1) << (addr % word_size);
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addr %= this->size;
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if (addr > this->size) {
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fprintf(stderr, "Invalid write address %lx\n", addr);
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exit(EXIT_FAILURE);
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}
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uint8_t *base = this->data + (addr / word_size) * word_size;
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uint8_t *base = this->data + (addr / word_size) * word_size;
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for (int i = 0; i < word_size; i++) {
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for (int i = 0; i < word_size; i++) {
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@ -26,10 +22,7 @@ void mm_t::write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size)
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std::vector<char> mm_t::read(uint64_t addr)
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std::vector<char> mm_t::read(uint64_t addr)
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{
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{
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if (addr > this->size) {
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addr %= this->size;
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fprintf(stderr, "Invalid read address %lx\n", addr);
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exit(EXIT_FAILURE);
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}
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uint8_t *base = this->data + addr;
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uint8_t *base = this->data + addr;
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return std::vector<char>(base, base + word_size);
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return std::vector<char>(base, base + word_size);
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@ -1 +1 @@
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Subproject commit 0204a9679bf1c2e79e6e603fd555abaf9892d0f5
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Subproject commit ed6b53a337af917f48fe6a10a3a1097bc542fe55
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@ -1 +1 @@
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Subproject commit 30ee6af52cada4fd8579f0654983ac73c1869473
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Subproject commit 7448c2726721b0260ce56e1dfc03d6f7786a2f9b
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@ -1 +1 @@
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Subproject commit 5fd945be6d791a189503cd3a91c22b191a32739c
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Subproject commit 4cacd6c014069761cacfed4f7d2c607b8db444d4
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2
rocket
2
rocket
@ -1 +1 @@
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Subproject commit 2b96ef2a00cba93ee7a72ac8f7d740dcde70ec52
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Subproject commit 679c9148da9cfdfff292958ebc2cb451f5787b6e
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@ -243,7 +243,7 @@ class DefaultConfig extends Config (
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maxClientsPerPort = site(NBanksPerMemoryChannel),
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maxClientsPerPort = site(NBanksPerMemoryChannel),
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dataBeats = site(MIFDataBeats))
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dataBeats = site(MIFDataBeats))
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case TLKey("L2toMMIO") => {
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case TLKey("L2toMMIO") => {
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val addrMap = new AddrHashMap(site(GlobalAddrMap))
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val addrMap = globalAddrHashMap
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TileLinkParameters(
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TileLinkParameters(
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coherencePolicy = new MICoherence(
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coherencePolicy = new MICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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@ -266,6 +266,7 @@ class DefaultConfig extends Config (
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case UseHtifClockDiv => true
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case UseHtifClockDiv => true
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case ConfigString => makeConfigString()
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case ConfigString => makeConfigString()
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case GlobalAddrMap => globalAddrMap
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case GlobalAddrMap => globalAddrMap
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case GlobalAddrHashMap => globalAddrHashMap
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case _ => throw new CDEMatchError
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case _ => throw new CDEMatchError
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}},
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}},
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knobValues = {
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knobValues = {
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@ -96,7 +96,7 @@ object TopUtils {
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rom.order(java.nio.ByteOrder.LITTLE_ENDIAN)
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rom.order(java.nio.ByteOrder.LITTLE_ENDIAN)
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// for now, have the reset vector jump straight to memory
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// for now, have the reset vector jump straight to memory
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val addrHashMap = new AddrHashMap(p(GlobalAddrMap))
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val addrHashMap = p(GlobalAddrHashMap)
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val resetToMemDist = addrHashMap("mem").start - p(ResetVector)
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val resetToMemDist = addrHashMap("mem").start - p(ResetVector)
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require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
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require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
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val configStringAddr = p(ResetVector).toInt + rom.capacity
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val configStringAddr = p(ResetVector).toInt + rom.capacity
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@ -181,7 +181,7 @@ class Uncore(implicit val p: Parameters) extends Module
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}
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}
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val addrMap = p(GlobalAddrMap)
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val addrMap = p(GlobalAddrMap)
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val addrHashMap = new AddrHashMap(addrMap)
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val addrHashMap = p(GlobalAddrHashMap)
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val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
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val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
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scrFile.io.smi <> htif.io.scr
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scrFile.io.smi <> htif.io.scr
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// scrFile.io.scr <> (... your SCR connections ...)
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// scrFile.io.scr <> (... your SCR connections ...)
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@ -251,7 +251,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
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val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
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}
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}
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val addrHashMap = new AddrHashMap(p(GlobalAddrMap))
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val addrHashMap = p(GlobalAddrHashMap)
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// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
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// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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@ -21,12 +21,12 @@ class WithGroundTest extends Config(
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maxClientXacts = max(
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maxClientXacts = max(
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site(NMSHRs) + 1,
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site(NMSHRs) + 1,
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxClientsPerPort = 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBits = site(CacheBlockBytes)*8)
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dataBits = site(CacheBlockBytes)*8)
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case BuildTiles => {
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case BuildTiles => {
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TestGeneration.addSuite(new AssemblyGroundTestSuite)
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TestGeneration.addSuite(DefaultTestSuites.rvall("p"))
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TestGeneration.addSuite(new BenchmarkGroundTestSuite)
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TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
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(0 until site(NTiles)).map { i =>
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(0 until site(NTiles)).map { i =>
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(r: Bool, p: Parameters) =>
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(r: Bool, p: Parameters) =>
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Module(new GroundTestTile(i, r)
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Module(new GroundTestTile(i, r)
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@ -35,6 +35,7 @@ class WithGroundTest extends Config(
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}
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}
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case GroundTestMaxXacts => 1
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case GroundTestMaxXacts => 1
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case GroundTestCSRs => Nil
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case GroundTestCSRs => Nil
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case TohostAddrs => Seq("80001000", "80001300").map(s => BigInt(s, 16))
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case RoccNCSRs => site(GroundTestCSRs).size
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case RoccNCSRs => site(GroundTestCSRs).size
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case UseFPU => false
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case UseFPU => false
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case _ => throw new CDEMatchError
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case _ => throw new CDEMatchError
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@ -46,7 +47,7 @@ class WithMemtest extends Config(
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case GenerateUncached => true
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case GenerateUncached => true
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case GenerateCached => true
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case GenerateCached => true
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case MaxGenerateRequests => 128
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case MaxGenerateRequests => 128
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case GeneratorStartAddress => 0
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case GeneratorStartAddress => site(GlobalAddrHashMap)("mem").start
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case BuildGroundTest =>
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case BuildGroundTest =>
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(id: Int, p: Parameters) => Module(new GeneratorTest(id)(p))
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(id: Int, p: Parameters) => Module(new GeneratorTest(id)(p))
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case _ => throw new CDEMatchError
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case _ => throw new CDEMatchError
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@ -30,25 +30,6 @@ run-$makeTargetName-debug: $$(addprefix $$(output_dir)/, $$(addsuffix .vpd, $$($
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"""
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"""
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}
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}
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trait GroundTestSuite extends RocketTestSuite {
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override def postScript = s"""
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$$(addprefix $$(output_dir)/, $$(addsuffix .hex, $$($makeTargetName))):
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\tmkdir -p $$(output_dir)
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\ttouch $$@
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$$(addprefix $$(output_dir)/, $$($makeTargetName)):
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\tmkdir -p $$(output_dir)
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\ttouch $$@
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run-$makeTargetName: $$(addprefix $$(output_dir)/, $$(addsuffix .out, $$($makeTargetName)))
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\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if /\\*{3}(.{8})\\*{3}(.*)/' $$^; echo;
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run-$makeTargetName-debug: $$(addprefix $$(output_dir)/, $$(addsuffix .vpd, $$($makeTargetName)))
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\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if /\\*{3}(.{8})\\*{3}(.*)/' $$(patsubst %.vpd,%.out,$$^); echo;
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"""
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}
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class AssemblyTestSuite(makePrefix: String, toolsPrefix: String, val names: LinkedHashSet[String])(val envName: String) extends RocketTestSuite {
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class AssemblyTestSuite(makePrefix: String, toolsPrefix: String, val names: LinkedHashSet[String])(val envName: String) extends RocketTestSuite {
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val dir = "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa"
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val dir = "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa"
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val makeTargetName = makePrefix + "-" + envName + "-asm-tests"
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val makeTargetName = makePrefix + "-" + envName + "-asm-tests"
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@ -61,18 +42,6 @@ class BenchmarkTestSuite(makePrefix: String, val dir: String, val names: LinkedH
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override def toString = s"$makeTargetName = \\\n" + names.map(n => s"\t$n.riscv").mkString(" \\\n") + postScript
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override def toString = s"$makeTargetName = \\\n" + names.map(n => s"\t$n.riscv").mkString(" \\\n") + postScript
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}
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}
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class AssemblyGroundTestSuite extends AssemblyTestSuite("","",LinkedHashSet())("") with GroundTestSuite {
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override val dir = ""
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override val names = LinkedHashSet[String]()
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override val makeTargetName = "unit-test"
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override def toString = s"$makeTargetName = unit-test\\\n" + postScript
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}
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class BenchmarkGroundTestSuite extends BenchmarkTestSuite("", "", LinkedHashSet()) with GroundTestSuite {
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override val makeTargetName = "unit-bmark-tests"
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override def toString = s"$makeTargetName = unit-test\\\n" + postScript
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}
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object TestGeneration extends FileSystemUtilities{
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object TestGeneration extends FileSystemUtilities{
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import scala.collection.mutable.HashMap
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import scala.collection.mutable.HashMap
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val asmSuites = new LinkedHashMap[String,AssemblyTestSuite]()
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val asmSuites = new LinkedHashMap[String,AssemblyTestSuite]()
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@ -165,6 +134,9 @@ object DefaultTestSuites {
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val rv64miNames = rv32miNames
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val rv64miNames = rv32miNames
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val rv64mi = new AssemblyTestSuite("rv64mi", "rv64mi", rv64miNames)(_)
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val rv64mi = new AssemblyTestSuite("rv64mi", "rv64mi", rv64miNames)(_)
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val rvallNames = LinkedHashSet("empty")
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val rvall = new AssemblyTestSuite("rvall", "rvall", rvallNames)(_)
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// TODO: "rv64ui-pm-lrsc", "rv64mi-pm-ipi",
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// TODO: "rv64ui-pm-lrsc", "rv64mi-pm-ipi",
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val rv64u = List(rv64ui, rv64um, rv64ua)
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val rv64u = List(rv64ui, rv64um, rv64ua)
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@ -173,6 +145,10 @@ object DefaultTestSuites {
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val bmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
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val bmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
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"median", "multiply", "qsort", "towers", "vvadd", "mm", "dhrystone", "spmv", "mt-vvadd", "mt-matmul"))
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"median", "multiply", "qsort", "towers", "vvadd", "mm", "dhrystone", "spmv", "mt-vvadd", "mt-matmul"))
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val emptyBmarks = new BenchmarkTestSuite("empty",
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"$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks",
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LinkedHashSet("empty"))
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val mtBmarks = new BenchmarkTestSuite("mt", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/mt",
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val mtBmarks = new BenchmarkTestSuite("mt", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/mt",
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LinkedHashSet(((0 to 4).map("vvadd"+_) ++
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LinkedHashSet(((0 to 4).map("vvadd"+_) ++
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List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az",
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List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az",
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit c775dc2c3d62240d89a74153c8e543a93e4834a9
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Subproject commit 8e21cc781f5fd1fdfd94a579fb5a1392ed664e99
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