From 487d0b356eebc7f80eb549174b8c14ec37ebccd1 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 2 May 2016 18:34:27 -0700 Subject: [PATCH] fixes to get groundtest working with priv-1.9 changes --- csrc/mm.cc | 11 ++------- groundtest | 2 +- junctions | 2 +- riscv-tools | 2 +- rocket | 2 +- src/main/scala/Configs.scala | 3 ++- src/main/scala/RocketChip.scala | 6 ++--- src/main/scala/TestConfigs.scala | 9 ++++---- src/main/scala/Testing.scala | 38 ++++++-------------------------- uncore | 2 +- 10 files changed, 24 insertions(+), 53 deletions(-) diff --git a/csrc/mm.cc b/csrc/mm.cc index caad38dd..571099da 100644 --- a/csrc/mm.cc +++ b/csrc/mm.cc @@ -10,11 +10,7 @@ void mm_t::write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size) { strb &= ((1 << size) - 1) << (addr % word_size); - - if (addr > this->size) { - fprintf(stderr, "Invalid write address %lx\n", addr); - exit(EXIT_FAILURE); - } + addr %= this->size; uint8_t *base = this->data + (addr / word_size) * word_size; for (int i = 0; i < word_size; i++) { @@ -26,10 +22,7 @@ void mm_t::write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size) std::vector mm_t::read(uint64_t addr) { - if (addr > this->size) { - fprintf(stderr, "Invalid read address %lx\n", addr); - exit(EXIT_FAILURE); - } + addr %= this->size; uint8_t *base = this->data + addr; return std::vector(base, base + word_size); diff --git a/groundtest b/groundtest index 0204a967..ed6b53a3 160000 --- a/groundtest +++ b/groundtest @@ -1 +1 @@ -Subproject commit 0204a9679bf1c2e79e6e603fd555abaf9892d0f5 +Subproject commit ed6b53a337af917f48fe6a10a3a1097bc542fe55 diff --git a/junctions b/junctions index 30ee6af5..7448c272 160000 --- a/junctions +++ b/junctions @@ -1 +1 @@ -Subproject commit 30ee6af52cada4fd8579f0654983ac73c1869473 +Subproject commit 7448c2726721b0260ce56e1dfc03d6f7786a2f9b diff --git a/riscv-tools b/riscv-tools index 5fd945be..4cacd6c0 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 5fd945be6d791a189503cd3a91c22b191a32739c +Subproject commit 4cacd6c014069761cacfed4f7d2c607b8db444d4 diff --git a/rocket b/rocket index 2b96ef2a..679c9148 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 2b96ef2a00cba93ee7a72ac8f7d740dcde70ec52 +Subproject commit 679c9148da9cfdfff292958ebc2cb451f5787b6e diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 76124253..5c2fa6d5 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -243,7 +243,7 @@ class DefaultConfig extends Config ( maxClientsPerPort = site(NBanksPerMemoryChannel), dataBeats = site(MIFDataBeats)) case TLKey("L2toMMIO") => { - val addrMap = new AddrHashMap(site(GlobalAddrMap)) + val addrMap = globalAddrHashMap TileLinkParameters( coherencePolicy = new MICoherence( new NullRepresentation(site(NBanksPerMemoryChannel))), @@ -266,6 +266,7 @@ class DefaultConfig extends Config ( case UseHtifClockDiv => true case ConfigString => makeConfigString() case GlobalAddrMap => globalAddrMap + case GlobalAddrHashMap => globalAddrHashMap case _ => throw new CDEMatchError }}, knobValues = { diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 75ef0eb2..06c37e17 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -96,7 +96,7 @@ object TopUtils { rom.order(java.nio.ByteOrder.LITTLE_ENDIAN) // for now, have the reset vector jump straight to memory - val addrHashMap = new AddrHashMap(p(GlobalAddrMap)) + val addrHashMap = p(GlobalAddrHashMap) val resetToMemDist = addrHashMap("mem").start - p(ResetVector) require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12)) val configStringAddr = p(ResetVector).toInt + rom.capacity @@ -181,7 +181,7 @@ class Uncore(implicit val p: Parameters) extends Module } val addrMap = p(GlobalAddrMap) - val addrHashMap = new AddrHashMap(addrMap) + val addrHashMap = p(GlobalAddrHashMap) val scrFile = Module(new SCRFile("UNCORE_SCR", 0)) scrFile.io.smi <> htif.io.scr // scrFile.io.scr <> (... your SCR connections ...) @@ -251,7 +251,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"})) } - val addrHashMap = new AddrHashMap(p(GlobalAddrMap)) + val addrHashMap = p(GlobalAddrHashMap) // Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory // Cached ports are first in client list, making sharerToClientId just an indentity function diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala index 88479f6f..72cc4c0b 100644 --- a/src/main/scala/TestConfigs.scala +++ b/src/main/scala/TestConfigs.scala @@ -21,12 +21,12 @@ class WithGroundTest extends Config( maxClientXacts = max( site(NMSHRs) + 1, if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)), - maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2, + maxClientsPerPort = 2, maxManagerXacts = site(NAcquireTransactors) + 2, dataBits = site(CacheBlockBytes)*8) case BuildTiles => { - TestGeneration.addSuite(new AssemblyGroundTestSuite) - TestGeneration.addSuite(new BenchmarkGroundTestSuite) + TestGeneration.addSuite(DefaultTestSuites.rvall("p")) + TestGeneration.addSuite(DefaultTestSuites.emptyBmarks) (0 until site(NTiles)).map { i => (r: Bool, p: Parameters) => Module(new GroundTestTile(i, r) @@ -35,6 +35,7 @@ class WithGroundTest extends Config( } case GroundTestMaxXacts => 1 case GroundTestCSRs => Nil + case TohostAddrs => Seq("80001000", "80001300").map(s => BigInt(s, 16)) case RoccNCSRs => site(GroundTestCSRs).size case UseFPU => false case _ => throw new CDEMatchError @@ -46,7 +47,7 @@ class WithMemtest extends Config( case GenerateUncached => true case GenerateCached => true case MaxGenerateRequests => 128 - case GeneratorStartAddress => 0 + case GeneratorStartAddress => site(GlobalAddrHashMap)("mem").start case BuildGroundTest => (id: Int, p: Parameters) => Module(new GeneratorTest(id)(p)) case _ => throw new CDEMatchError diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala index b7064b5e..e4134433 100644 --- a/src/main/scala/Testing.scala +++ b/src/main/scala/Testing.scala @@ -30,25 +30,6 @@ run-$makeTargetName-debug: $$(addprefix $$(output_dir)/, $$(addsuffix .vpd, $$($ """ } -trait GroundTestSuite extends RocketTestSuite { - override def postScript = s""" - -$$(addprefix $$(output_dir)/, $$(addsuffix .hex, $$($makeTargetName))): -\tmkdir -p $$(output_dir) -\ttouch $$@ - -$$(addprefix $$(output_dir)/, $$($makeTargetName)): -\tmkdir -p $$(output_dir) -\ttouch $$@ - -run-$makeTargetName: $$(addprefix $$(output_dir)/, $$(addsuffix .out, $$($makeTargetName))) -\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if /\\*{3}(.{8})\\*{3}(.*)/' $$^; echo; - -run-$makeTargetName-debug: $$(addprefix $$(output_dir)/, $$(addsuffix .vpd, $$($makeTargetName))) -\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if /\\*{3}(.{8})\\*{3}(.*)/' $$(patsubst %.vpd,%.out,$$^); echo; - """ -} - class AssemblyTestSuite(makePrefix: String, toolsPrefix: String, val names: LinkedHashSet[String])(val envName: String) extends RocketTestSuite { val dir = "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa" val makeTargetName = makePrefix + "-" + envName + "-asm-tests" @@ -61,18 +42,6 @@ class BenchmarkTestSuite(makePrefix: String, val dir: String, val names: LinkedH override def toString = s"$makeTargetName = \\\n" + names.map(n => s"\t$n.riscv").mkString(" \\\n") + postScript } -class AssemblyGroundTestSuite extends AssemblyTestSuite("","",LinkedHashSet())("") with GroundTestSuite { - override val dir = "" - override val names = LinkedHashSet[String]() - override val makeTargetName = "unit-test" - override def toString = s"$makeTargetName = unit-test\\\n" + postScript -} - -class BenchmarkGroundTestSuite extends BenchmarkTestSuite("", "", LinkedHashSet()) with GroundTestSuite { - override val makeTargetName = "unit-bmark-tests" - override def toString = s"$makeTargetName = unit-test\\\n" + postScript -} - object TestGeneration extends FileSystemUtilities{ import scala.collection.mutable.HashMap val asmSuites = new LinkedHashMap[String,AssemblyTestSuite]() @@ -165,6 +134,9 @@ object DefaultTestSuites { val rv64miNames = rv32miNames val rv64mi = new AssemblyTestSuite("rv64mi", "rv64mi", rv64miNames)(_) + val rvallNames = LinkedHashSet("empty") + val rvall = new AssemblyTestSuite("rvall", "rvall", rvallNames)(_) + // TODO: "rv64ui-pm-lrsc", "rv64mi-pm-ipi", val rv64u = List(rv64ui, rv64um, rv64ua) @@ -173,6 +145,10 @@ object DefaultTestSuites { val bmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet( "median", "multiply", "qsort", "towers", "vvadd", "mm", "dhrystone", "spmv", "mt-vvadd", "mt-matmul")) + val emptyBmarks = new BenchmarkTestSuite("empty", + "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", + LinkedHashSet("empty")) + val mtBmarks = new BenchmarkTestSuite("mt", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/mt", LinkedHashSet(((0 to 4).map("vvadd"+_) ++ List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az", diff --git a/uncore b/uncore index c775dc2c..8e21cc78 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit c775dc2c3d62240d89a74153c8e543a93e4834a9 +Subproject commit 8e21cc781f5fd1fdfd94a579fb5a1392ed664e99