riscv/rocket-chip
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fixes to get groundtest working with priv-1.9 changes

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This commit is contained in:
Howard Mao
2016-05-02 18:34:27 -07:00
parent c7c8ae5468
commit 487d0b356e
10 changed files with 24 additions and 53 deletions
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3
src/main/scala/Configs.scala
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@ -243,7 +243,7 @@ class DefaultConfig extends Config (
maxClientsPerPort = site(NBanksPerMemoryChannel),
dataBeats = site(MIFDataBeats))
case TLKey("L2toMMIO") => {
val addrMap = new AddrHashMap(site(GlobalAddrMap))
val addrMap = globalAddrHashMap
TileLinkParameters(
coherencePolicy = new MICoherence(
new NullRepresentation(site(NBanksPerMemoryChannel))),
@ -266,6 +266,7 @@ class DefaultConfig extends Config (
case UseHtifClockDiv => true
case ConfigString => makeConfigString()
case GlobalAddrMap => globalAddrMap
case GlobalAddrHashMap => globalAddrHashMap
case _ => throw new CDEMatchError
}},
knobValues = {