riscv/rocket-chip
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Address some PMP critical paths

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This commit is contained in:
Andrew Waterman 2017-03-15 15:22:39 -07:00
parent 03fb334c4c
commit 487b8db5ef
3 changed files with 4 additions and 4 deletions
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2
src/main/scala/rocket/DCache.scala
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@ -105,7 +105,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
// address translation // address translation
val tlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries)) val tlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> tlb.io.ptw io.ptw <> tlb.io.ptw
tlb.io.req.valid := s1_valid_masked && (s1_readwrite || s1_sfence) tlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence)
tlb.io.req.bits.sfence.valid := s1_sfence tlb.io.req.bits.sfence.valid := s1_sfence
tlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0) tlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
tlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1) tlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1)

4
src/main/scala/rocket/Frontend.scala
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@ -140,8 +140,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
icache.io.req.bits.addr := io.cpu.npc icache.io.req.bits.addr := io.cpu.npc
icache.io.invalidate := io.cpu.flush_icache icache.io.invalidate := io.cpu.flush_icache
icache.io.s1_paddr := tlb.io.resp.paddr icache.io.s1_paddr := tlb.io.resp.paddr
icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss
icache.io.s2_kill := s2_speculative && !s2_cacheable icache.io.s2_kill := s2_speculative && !s2_cacheable || s2_xcpt_if
icache.io.resp.ready := !stall && !s1_same_block icache.io.resp.ready := !stall && !s1_same_block
io.cpu.resp.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill || s2_xcpt_if) io.cpu.resp.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill || s2_xcpt_if)

2
src/main/scala/rocket/NBDcache.scala
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@ -699,7 +699,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries)) val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> dtlb.io.ptw io.ptw <> dtlb.io.ptw
dtlb.io.req.valid := s1_valid_masked && (s1_readwrite || s1_sfence) dtlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence)
dtlb.io.req.bits.sfence.valid := s1_sfence dtlb.io.req.bits.sfence.valid := s1_sfence
dtlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0) dtlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
dtlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1) dtlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1)