From 487b8db5ef967916c5a8803aab0697e9827ac34c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 15 Mar 2017 15:22:39 -0700 Subject: [PATCH] Address some PMP critical paths --- src/main/scala/rocket/DCache.scala | 2 +- src/main/scala/rocket/Frontend.scala | 4 ++-- src/main/scala/rocket/NBDcache.scala | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index a1cbdbe2..5504d0c2 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -105,7 +105,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { // address translation val tlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries)) io.ptw <> tlb.io.ptw - tlb.io.req.valid := s1_valid_masked && (s1_readwrite || s1_sfence) + tlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence) tlb.io.req.bits.sfence.valid := s1_sfence tlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0) tlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index 501072db..dd8653b6 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -140,8 +140,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) icache.io.req.bits.addr := io.cpu.npc icache.io.invalidate := io.cpu.flush_icache icache.io.s1_paddr := tlb.io.resp.paddr - icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss - icache.io.s2_kill := s2_speculative && !s2_cacheable + icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss + icache.io.s2_kill := s2_speculative && !s2_cacheable || s2_xcpt_if icache.io.resp.ready := !stall && !s1_same_block io.cpu.resp.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill || s2_xcpt_if) diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala index d7b9e05c..9ec9ec4f 100644 --- a/src/main/scala/rocket/NBDcache.scala +++ b/src/main/scala/rocket/NBDcache.scala @@ -699,7 +699,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries)) io.ptw <> dtlb.io.ptw - dtlb.io.req.valid := s1_valid_masked && (s1_readwrite || s1_sfence) + dtlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence) dtlb.io.req.bits.sfence.valid := s1_sfence dtlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0) dtlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1)