riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Address some PMP critical paths

Browse Source
This commit is contained in:
Andrew Waterman
2017-03-15 15:22:39 -07:00
parent 03fb334c4c
commit 487b8db5ef
3 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/rocket/Frontend.scala
View File

@ -140,8 +140,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
icache.io.req.bits.addr := io.cpu.npc
icache.io.invalidate := io.cpu.flush_icache
icache.io.s1_paddr := tlb.io.resp.paddr
icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss
icache.io.s2_kill := s2_speculative && !s2_cacheable
icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss
icache.io.s2_kill := s2_speculative && !s2_cacheable || s2_xcpt_if
icache.io.resp.ready := !stall && !s1_same_block
io.cpu.resp.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill || s2_xcpt_if)