riscv/rocket-chip
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Address some PMP critical paths

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This commit is contained in:
Andrew Waterman
2017-03-15 15:22:39 -07:00
parent 03fb334c4c
commit 487b8db5ef
3 changed files with 4 additions and 4 deletions
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src/main/scala/rocket/DCache.scala
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@ -105,7 +105,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
// address translation
val tlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> tlb.io.ptw
tlb.io.req.valid := s1_valid_masked && (s1_readwrite || s1_sfence)
tlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence)
tlb.io.req.bits.sfence.valid := s1_sfence
tlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
tlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1)