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synchronizers: Correctly pass the width through

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This commit is contained in:
Megan Wachs 2017-08-30 11:50:25 -07:00
parent c473538e36
commit 483e63da19
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/util/SynchronizingReg.scala
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@ -38,7 +38,7 @@ object AbstractSynchronizerReg {
}
}
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w, sync) {
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
@ -63,7 +63,7 @@ object AsyncResetSynchronizerShiftReg {
in, sync, name)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w, sync) {
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"