From 483e63da19f061e7ecbce51324f8df315295c1ec Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 11:50:25 -0700
Subject: [PATCH] synchronizers: Correctly pass the width through

---
 src/main/scala/util/SynchronizingReg.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index c803ac82..e81157d5 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -38,7 +38,7 @@ object AbstractSynchronizerReg {
   }
 }
 
-class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
+class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w, sync) {
 
   override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
 
@@ -63,7 +63,7 @@ object AsyncResetSynchronizerShiftReg {
       in, sync, name)
 }
 
-class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg {
+class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w, sync) {
 
   override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"