riscv/rocket-chip
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rocket: link itim to its cpu

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This commit is contained in:
Wesley W. Terpstra
2017-06-28 14:53:09 -07:00
parent e6c2d446cc
commit 48390ed604
3 changed files with 14 additions and 5 deletions
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11
src/main/scala/rocket/ICache.scala
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@ -35,12 +35,19 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
val addr = UInt(width = vaddrBits)
}
class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parameters) extends LazyModule {
class ICache(val icacheParams: ICacheParams, val hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule {
lazy val module = new ICacheModule(this)
val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
val device = new SimpleDevice("itim", Seq("sifive,itim0")) {
override def describe(resources: ResourceBindings): Description = {
val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label))))
val Description(name, mapping) = super.describe(resources)
Description(name, mapping ++ extra)
}
}
val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
val device = new SimpleDevice("itim", Seq("sifive,itim0"))
val slaveNode = icacheParams.itimAddr.map { itimAddr =>
val wordBytes = icacheParams.fetchBytes
TLManagerNode(Seq(TLManagerPortParameters(