From 48390ed604e12dbcb1b119cb2d4eb1c645ea8f7e Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 28 Jun 2017 14:53:09 -0700
Subject: [PATCH] rocket: link itim to its cpu

---
 src/main/scala/rocket/Frontend.scala    |  7 ++++---
 src/main/scala/rocket/ICache.scala      | 11 +++++++++--
 src/main/scala/rocket/RocketTiles.scala |  1 +
 3 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala
index 35642a23..0faad869 100644
--- a/src/main/scala/rocket/Frontend.scala
+++ b/src/main/scala/rocket/Frontend.scala
@@ -53,9 +53,9 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
   val perf = new FrontendPerfEvents().asInput
 }
 
-class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
+class Frontend(val icacheParams: ICacheParams, hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule {
   lazy val module = new FrontendModule(this)
-  val icache = LazyModule(new ICache(icacheParams, hartid))
+  val icache = LazyModule(new ICache(icacheParams, hartid, owner))
   val masterNode = TLOutputNode()
   val slaveNode = TLInputNode()
 
@@ -184,7 +184,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
 /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
 trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
   val module: HasICacheFrontendModule
-  val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int))
+  def itimOwner : Option[Device] = None
+  val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int, itimOwner))
   val hartid: Int
   tileBus.node := frontend.masterNode
   nPTWPorts += 1
diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala
index dfb240f4..ec093623 100644
--- a/src/main/scala/rocket/ICache.scala
+++ b/src/main/scala/rocket/ICache.scala
@@ -35,12 +35,19 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
   val addr = UInt(width = vaddrBits)
 }
 
-class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parameters) extends LazyModule {
+class ICache(val icacheParams: ICacheParams, val hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule {
   lazy val module = new ICacheModule(this)
   val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
 
+  val device = new SimpleDevice("itim", Seq("sifive,itim0")) {
+      override def describe(resources: ResourceBindings): Description = {
+      val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label))))
+      val Description(name, mapping) = super.describe(resources)
+      Description(name, mapping ++ extra)
+    }
+  }
+
   val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
-  val device = new SimpleDevice("itim", Seq("sifive,itim0"))
   val slaveNode = icacheParams.itimAddr.map { itimAddr =>
     val wordBytes = icacheParams.fetchBytes
     TLManagerNode(Seq(TLManagerPortParameters(
diff --git a/src/main/scala/rocket/RocketTiles.scala b/src/main/scala/rocket/RocketTiles.scala
index 4e5fccad..ab118915 100644
--- a/src/main/scala/rocket/RocketTiles.scala
+++ b/src/main/scala/rocket/RocketTiles.scala
@@ -91,6 +91,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
   }
 
   override def dtimOwner = Some(cpuDevice)
+  override def itimOwner = Some(cpuDevice)
 
   val intcDevice = new Device {
     def describe(resources: ResourceBindings): Description = {