[WIP] Move RocketTestSuite generation into RocketchipGenerator
This commit is contained in:
Henry Cook
parent
64fe010369
commit
47c5d1a992
@ -13,8 +13,6 @@ import rocket._
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import rocket.Util._
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import util.ConfigUtils._
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import rocketchip.{GlobalAddrMap, NCoreplexExtClients}
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import scala.collection.mutable.{LinkedHashSet, ListBuffer}
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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class BaseCoreplexConfig extends Config (
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@ -71,28 +69,6 @@ class BaseCoreplexConfig extends Config (
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case NUncachedTileLinkPorts => 1
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//Tile Constants
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case BuildTiles => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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site(FPUKey) foreach { case cfg =>
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if (site(XLen) == 32) {
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TestGeneration.addSuites(env.map(rv32ufNoDiv))
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} else {
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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if (cfg.divSqrt) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64ud))
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}
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}
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}
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if (site(UseAtomics)) TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
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if (site(UseCompressed)) TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64uc else rv32uc))
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val (rvi, rvu) =
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if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u)
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else ((if (site(UseVM)) rv32i else rv32pi), rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(benchmarks)
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List.tabulate(site(NTiles)){ i => (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({
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case TileId => i
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@ -187,32 +163,6 @@ class BaseCoreplexConfig extends Config (
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case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case EnableL2Logging => false
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case RegressionTestNames => LinkedHashSet(
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"rv64ud-v-fcvt",
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"rv64ud-p-fdiv",
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"rv64ud-v-fadd",
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"rv64uf-v-fadd",
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"rv64um-v-mul",
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"rv64mi-p-breakpoint",
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"rv64uc-v-rvc",
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"rv64ud-v-structural",
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"rv64si-p-wfi",
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"rv64um-v-divw",
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"rv64ua-v-lrsc",
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"rv64ui-v-fence_i",
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"rv64ud-v-fcvt_w",
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"rv64uf-v-fmin",
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"rv64ui-v-sb",
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"rv64ua-v-amomax_d",
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"rv64ud-v-move",
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"rv64ud-v-fclass",
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"rv64ua-v-amoand_d",
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"rv64ua-v-amoxor_d",
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"rv64si-p-sbreak",
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"rv64ud-v-fmadd",
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"rv64uf-v-ldst",
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"rv64um-v-mulh",
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"rv64si-p-dirty")
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case _ => throw new CDEMatchError
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}},
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knobValues = {
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@ -327,14 +277,6 @@ class WithRV32 extends Config(
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(pname,site,here) => pname match {
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case XLen => 32
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case FPUKey => Some(FPUConfig(divSqrt = false))
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case RegressionTestNames => LinkedHashSet(
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"rv32mi-p-ma_addr",
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"rv32mi-p-csr",
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"rv32ui-p-sh",
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"rv32ui-p-lh",
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"rv32uc-p-rvc",
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"rv32mi-p-sbreak",
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"rv32ui-p-sll")
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case _ => throw new CDEMatchError
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}
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)
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@ -7,8 +7,6 @@ import uncore.coherence._
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import uncore.agents._
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import uncore.devices.NTiles
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import junctions._
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import scala.collection.mutable.LinkedHashSet
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import scala.collection.immutable.HashMap
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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import scala.math.max
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import coreplex._
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@ -125,7 +123,6 @@ class WithGroundTest extends Config(
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case FPUKey => None
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case UseAtomics => false
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case UseCompressed => false
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case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
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case _ => throw new CDEMatchError
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})
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@ -8,7 +8,7 @@ import junctions._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.devices._
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import util.ParameterizedBundle
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import util.{ParameterizedBundle, ConfigStringOutput}
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import rocket._
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import rocket.Util._
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import coreplex._
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@ -3,121 +3,79 @@
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package rocketchip
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import Chisel._
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import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
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import cde._
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import coreplex._
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import java.io.{File, FileWriter}
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/** Representation of the information this Generator needs to collect from external sources. */
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case class ParsedInputNames(
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targetDir: String,
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topModuleProject: String,
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topModuleClass: String,
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configProject: String,
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configs: String) {
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val configClasses: Seq[String] = configs.split('_')
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val fullConfigClasses: Seq[String] = configClasses.map(configProject + "." + _)
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val fullTopModuleClass: String = topModuleProject + "." + topModuleClass
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}
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/** Common utilities we supply to all Generators. In particular, supplies the
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* canonical ways of building various JVM elaboration-time structures.
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*/
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trait HasGeneratorUtilities {
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def getConfig(names: ParsedInputNames): Config = {
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names.fullConfigClasses.foldRight(new Config()) { case (currentName, config) =>
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val currentConfig = try {
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Class.forName(currentName).newInstance.asInstanceOf[Config]
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} catch {
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case e: java.lang.ClassNotFoundException =>
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throwException(s"""Unable to find part "$currentName" from "${names.configs}", did you misspell it?""", e)
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}
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currentConfig ++ config
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}
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}
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def getParameters(names: ParsedInputNames): Parameters = getParameters(getConfig(names))
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def getParameters(config: Config): Parameters = Parameters.root(config.toInstance)
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import chisel3.internal.firrtl.Circuit
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def elaborate(names: ParsedInputNames, params: Parameters): Circuit = {
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val gen = () =>
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Class.forName(names.fullTopModuleClass)
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.getConstructor(classOf[cde.Parameters])
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.newInstance(params)
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.asInstanceOf[Module]
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Driver.elaborate(gen)
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}
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def writeOutputFile(targetDir: String, fname: String, contents: String): File = {
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val f = new File(targetDir, fname)
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val fw = new FileWriter(f)
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fw.write(contents)
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fw.close
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f
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}
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}
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/** Standardized command line interface for Scala entry point */
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trait Generator extends App with HasGeneratorUtilities {
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lazy val names: ParsedInputNames = {
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require(args.size == 5, "Usage: sbt> " +
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"run TargetDir TopModuleProjectName TopModuleName ConfigProjectName ConfigNameString")
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ParsedInputNames(
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targetDir = args(0),
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topModuleProject = args(1),
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topModuleClass = args(2),
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configProject = args(3),
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configs = args(4))
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}
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// Canonical ways of building various JVM elaboration-time structures
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lazy val td = names.targetDir
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lazy val config = getConfig(names)
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lazy val world = config.toInstance
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lazy val params = Parameters.root(world)
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lazy val circuit = elaborate(names, params)
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val longName: String // Exhaustive name used to interface with external build tool targets
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/** Output FIRRTL, which an external compiler can turn into Verilog. */
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def generateFirrtl {
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Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
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}
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/** Output software test Makefrags, which provide targets for integration testing. */
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def generateTestSuiteMakefrags {
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TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))
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writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Coreplex-specific test suites
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}
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/** Output Design Space Exploration knobs and constraints. */
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def generateDSEConstraints {
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writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE
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writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE
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}
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/** Output a global Parameter dump, which an external script can turn into Verilog headers. */
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def generateParameterDump {
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writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
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}
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/** Output a global ConfigString, for use by the RISC-V software ecosystem. */
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def generateConfigString {
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ConfigStringOutput.contents.foreach(c => writeOutputFile(td, s"${names.configs}.cfg", c)) // String for software
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}
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}
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object ConfigStringOutput {
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var contents: Option[String] = None
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}
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import rocket.{XLen, UseVM, UseAtomics, UseCompressed, FPUKey}
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import util.Generator
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import scala.collection.mutable.LinkedHashSet
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/** An example Generator */
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object RocketChipGenerator extends Generator
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{
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val rv64RegrTestNames = LinkedHashSet(
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"rv64ud-v-fcvt",
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"rv64ud-p-fdiv",
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"rv64ud-v-fadd",
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"rv64uf-v-fadd",
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"rv64um-v-mul",
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"rv64mi-p-breakpoint",
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"rv64uc-v-rvc",
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"rv64ud-v-structural",
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"rv64si-p-wfi",
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"rv64um-v-divw",
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"rv64ua-v-lrsc",
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"rv64ui-v-fence_i",
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"rv64ud-v-fcvt_w",
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"rv64uf-v-fmin",
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"rv64ui-v-sb",
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"rv64ua-v-amomax_d",
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"rv64ud-v-move",
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"rv64ud-v-fclass",
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"rv64ua-v-amoand_d",
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"rv64ua-v-amoxor_d",
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"rv64si-p-sbreak",
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"rv64ud-v-fmadd",
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"rv64uf-v-ldst",
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"rv64um-v-mulh",
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"rv64si-p-dirty")
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val rv32RegrTestNames = LinkedHashSet(
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"rv32mi-p-ma_addr",
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"rv32mi-p-csr",
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"rv32ui-p-sh",
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"rv32ui-p-lh",
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"rv32uc-p-rvc",
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"rv32mi-p-sbreak",
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"rv32ui-p-sll")
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override def addTestSuites {
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import DefaultTestSuites._
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val xlen = params(XLen)
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val vm = params(UseVM)
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val env = if (vm) List("p","v") else List("p")
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params(FPUKey) foreach { case cfg =>
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if (xlen == 32) {
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TestGeneration.addSuites(env.map(rv32ufNoDiv))
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} else {
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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if (cfg.divSqrt) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64ud))
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}
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}
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}
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if (params(UseAtomics)) TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
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if (params(UseCompressed)) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
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val (rvi, rvu) =
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if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
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else ((if (vm) rv32i else rv32pi), rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(benchmarks)
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TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
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}
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val longName = names.topModuleProject + "." + names.configs
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generateFirrtl
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generateTestSuiteMakefrags
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@ -1,12 +1,9 @@
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// See LICENSE for license details.
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package coreplex
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package rocketchip
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import Chisel._
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import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
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import cde.{Parameters, ParameterDump, Config, Field, CDEMatchError}
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case object RegressionTestNames extends Field[LinkedHashSet[String]]
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import scala.collection.mutable.{LinkedHashSet, LinkedHashMap}
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abstract class RocketTestSuite {
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val dir: String
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@ -175,6 +172,8 @@ object DefaultTestSuites {
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val emptyBmarks = new BenchmarkTestSuite("empty",
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"$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet.empty)
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val singleRegression = new RegressionTestSuite(LinkedHashSet("rv64iu-p-simple"))
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val mtBmarks = new BenchmarkTestSuite("mt", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/mt",
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LinkedHashSet(((0 to 4).map("vvadd"+_) ++
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List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az",
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@ -4,37 +4,32 @@ package unittest
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import Chisel._
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import cde.{Parameters, Config, CDEMatchError}
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import coreplex.{TestGeneration, DefaultTestSuites}
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import rocketchip.BaseConfig
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import rocketchip.{BaseConfig, BasePlatformConfig}
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class WithJunctionsUnitTests extends Config(
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(pname, site, here) => pname match {
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case UnitTests => (p: Parameters) => {
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TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
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TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
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Seq(
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case junctions.PAddrBits => 32
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case rocket.XLen => 64
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case UnitTests => (p: Parameters) => Seq(
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Module(new junctions.MultiWidthFifoTest),
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Module(new junctions.NastiMemoryDemuxTest()(p)),
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Module(new junctions.HastiTest()(p)))
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}
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case _ => throw new CDEMatchError
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})
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class JunctionsUnitTestConfig extends Config(new WithJunctionsUnitTests ++ new BasePlatformConfig)
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class WithUncoreUnitTests extends Config(
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(pname, site, here) => pname match {
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case rocketchip.NCoreplexExtClients => 0
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case uncore.tilelink.TLId => "L1toL2"
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case UnitTests => (p: Parameters) => {
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TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
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TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
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Seq(
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case UnitTests => (p: Parameters) => Seq(
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Module(new uncore.devices.ROMSlaveTest()(p)),
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Module(new uncore.devices.TileLinkRAMTest()(p)),
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Module(new uncore.tilelink2.TLFuzzRAMTest)
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)
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}
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Module(new uncore.tilelink2.TLFuzzRAMTest))
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case _ => throw new CDEMatchError
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}
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)
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class UnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithJunctionsUnitTests ++ new BaseConfig)
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class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new BaseConfig)
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125
src/main/scala/util/GeneratorUtils.scala
Normal file
125
src/main/scala/util/GeneratorUtils.scala
Normal file
@ -0,0 +1,125 @@
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// See LICENSE for license details.
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package util
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import Chisel._
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import cde._
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import java.io.{File, FileWriter}
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/** Representation of the information this Generator needs to collect from external sources. */
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case class ParsedInputNames(
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targetDir: String,
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topModuleProject: String,
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topModuleClass: String,
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configProject: String,
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configs: String) {
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val configClasses: Seq[String] = configs.split('_')
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val fullConfigClasses: Seq[String] = configClasses.map(configProject + "." + _)
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val fullTopModuleClass: String = topModuleProject + "." + topModuleClass
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}
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/** Common utilities we supply to all Generators. In particular, supplies the
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* canonical ways of building various JVM elaboration-time structures.
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*/
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trait HasGeneratorUtilities {
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def getConfig(names: ParsedInputNames): Config = {
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names.fullConfigClasses.foldRight(new Config()) { case (currentName, config) =>
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val currentConfig = try {
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Class.forName(currentName).newInstance.asInstanceOf[Config]
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} catch {
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case e: java.lang.ClassNotFoundException =>
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throwException(s"""Unable to find part "$currentName" from "${names.configs}", did you misspell it?""", e)
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}
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currentConfig ++ config
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}
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}
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def getParameters(names: ParsedInputNames): Parameters = getParameters(getConfig(names))
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def getParameters(config: Config): Parameters = Parameters.root(config.toInstance)
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import chisel3.internal.firrtl.Circuit
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def elaborate(names: ParsedInputNames, params: Parameters): Circuit = {
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val gen = () =>
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Class.forName(names.fullTopModuleClass)
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.getConstructor(classOf[cde.Parameters])
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.newInstance(params)
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.asInstanceOf[Module]
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Driver.elaborate(gen)
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}
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def writeOutputFile(targetDir: String, fname: String, contents: String): File = {
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val f = new File(targetDir, fname)
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val fw = new FileWriter(f)
|
||||
fw.write(contents)
|
||||
fw.close
|
||||
f
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/** Standardized command line interface for Scala entry point */
|
||||
trait Generator extends App with HasGeneratorUtilities {
|
||||
lazy val names: ParsedInputNames = {
|
||||
require(args.size == 5, "Usage: sbt> " +
|
||||
"run TargetDir TopModuleProjectName TopModuleName " +
|
||||
"ConfigProjectName ConfigNameString")
|
||||
ParsedInputNames(
|
||||
targetDir = args(0),
|
||||
topModuleProject = args(1),
|
||||
topModuleClass = args(2),
|
||||
configProject = args(3),
|
||||
configs = args(4))
|
||||
}
|
||||
|
||||
// Canonical ways of building various JVM elaboration-time structures
|
||||
lazy val td = names.targetDir
|
||||
lazy val config = getConfig(names)
|
||||
lazy val world = config.toInstance
|
||||
lazy val params = Parameters.root(world)
|
||||
lazy val circuit = elaborate(names, params)
|
||||
|
||||
val longName: String // Exhaustive name used to interface with external build tool targets
|
||||
|
||||
/** Output FIRRTL, which an external compiler can turn into Verilog. */
|
||||
def generateFirrtl {
|
||||
Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
|
||||
}
|
||||
|
||||
/** Output software test Makefrags, which provide targets for integration testing. */
|
||||
def generateTestSuiteMakefrags {
|
||||
addTestSuites
|
||||
writeOutputFile(td, s"$longName.d", rocketchip.TestGeneration.generateMakefrag) // Coreplex-specific test suites
|
||||
}
|
||||
|
||||
def addTestSuites {
|
||||
// TODO: better job of Makefrag generation
|
||||
// for non-RocketChip testing platforms
|
||||
import rocketchip.{DefaultTestSuites, TestGeneration}
|
||||
TestGeneration.addSuite(DefaultTestSuites.groundtest64("p"))
|
||||
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
|
||||
TestGeneration.addSuite(DefaultTestSuites.singleRegression)
|
||||
}
|
||||
|
||||
/** Output Design Space Exploration knobs and constraints. */
|
||||
def generateDSEConstraints {
|
||||
writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE
|
||||
writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE
|
||||
}
|
||||
|
||||
/** Output a global Parameter dump, which an external script can turn into Verilog headers. */
|
||||
def generateParameterDump {
|
||||
writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
|
||||
}
|
||||
|
||||
/** Output a global ConfigString, for use by the RISC-V software ecosystem. */
|
||||
def generateConfigString {
|
||||
ConfigStringOutput.contents.foreach(c => writeOutputFile(td, s"${names.configs}.cfg", c))
|
||||
}
|
||||
}
|
||||
|
||||
object ConfigStringOutput {
|
||||
var contents: Option[String] = None
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user