riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Give AsyncCrossing slave interfaces registers visibility into when they were written (#288)

Browse Source
This commit is contained in:
mwachs5 2016-09-14 00:17:26 -07:00 committed by Wesley W. Terpstra
parent bdb7b1de36
commit 47acbf928b
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/tilelink2/RegisterCrossing.scala
View File

@ -48,6 +48,7 @@ class RegisterWriteCrossingIO[T <: Data](gen: T) extends Bundle {
val slave_reset = Bool(INPUT)
val slave_allow = Bool(INPUT) // honour requests from the master
val slave_register = gen.asOutput
val slave_valid = Bool(OUTPUT) // is high on 1st cycle slave_register has a new value
}
class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
@ -65,6 +66,7 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
crossing.io.enq.bits := io.master_port.request.bits
io.slave_register := crossing.io.deq.bits
io.slave_valid := crossing.io.deq.valid
// If the slave is not operational, just drop the write.
val progress = crossing.io.enq.ready || !io.master_allow