From 47acbf928b3331b62a036edb3fc23657dfa56eaa Mon Sep 17 00:00:00 2001 From: mwachs5 Date: Wed, 14 Sep 2016 00:17:26 -0700 Subject: [PATCH] Give AsyncCrossing slave interfaces registers visibility into when they were written (#288) --- src/main/scala/uncore/tilelink2/RegisterCrossing.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/uncore/tilelink2/RegisterCrossing.scala b/src/main/scala/uncore/tilelink2/RegisterCrossing.scala index 36a5606e..cb66aca5 100644 --- a/src/main/scala/uncore/tilelink2/RegisterCrossing.scala +++ b/src/main/scala/uncore/tilelink2/RegisterCrossing.scala @@ -48,6 +48,7 @@ class RegisterWriteCrossingIO[T <: Data](gen: T) extends Bundle { val slave_reset = Bool(INPUT) val slave_allow = Bool(INPUT) // honour requests from the master val slave_register = gen.asOutput + val slave_valid = Bool(OUTPUT) // is high on 1st cycle slave_register has a new value } class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module { @@ -65,6 +66,7 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module { crossing.io.enq.bits := io.master_port.request.bits io.slave_register := crossing.io.deq.bits + io.slave_valid := crossing.io.deq.valid // If the slave is not operational, just drop the write. val progress = crossing.io.enq.ready || !io.master_allow