riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

make sure TLId set in Periphery

Browse Source
This commit is contained in:
Howard Mao 2016-08-15 13:58:23 -07:00
parent e939af88aa
commit 47a0c880a4
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/RocketChip.scala
View File

@ -125,7 +125,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
val io = new TopIO
val coreplex = p(BuildCoreplex)(p)
val periphery = Module(new Periphery)
val periphery = Module(new Periphery()(innerParams))
if (exportMMIO) { periphery.io.mmio_in.get <> coreplex.io.mmio.get }
periphery.io.mem_in <> coreplex.io.mem