riscv/rocket-chip
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make sure TLId set in Periphery

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This commit is contained in:
Howard Mao 2016-08-15 13:58:23 -07:00
parent e939af88aa
commit 47a0c880a4
1 changed files with 1 additions and 1 deletions
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src/main/scala/RocketChip.scala
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@ -125,7 +125,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
val io = new TopIO val io = new TopIO
val coreplex = p(BuildCoreplex)(p) val coreplex = p(BuildCoreplex)(p)
val periphery = Module(new Periphery) val periphery = Module(new Periphery()(innerParams))
if (exportMMIO) { periphery.io.mmio_in.get <> coreplex.io.mmio.get } if (exportMMIO) { periphery.io.mmio_in.get <> coreplex.io.mmio.get }
periphery.io.mem_in <> coreplex.io.mem periphery.io.mem_in <> coreplex.io.mem