riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

rocket: add an AXI master port into the chip

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-07-05 12:43:33 -07:00
parent 8ac7fa5544
commit 46fc9744e2
2 changed files with 15 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/Configs.scala
View File

@ -225,6 +225,7 @@ class BaseConfig extends Config (
case NExtMMIOAXIChannels => 0
case NExtMMIOAHBChannels => 0
case NExtMMIOTLChannels => 0
case NExtBusAXIChannels => 0
case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
case FDivSqrt => true
@ -255,7 +256,7 @@ class BaseConfig extends Config (
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NUncachedTileLinkPorts),
nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts),
maxClientXacts = max_int(
// L1 cache
site(NMSHRs) + 1 /* IOMSHR */,