riscv/rocket-chip
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fix fence.i for associative caches

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This commit is contained in:
Andrew Waterman 2012-03-15 21:23:21 -07:00
parent 2b0bc8df2b
commit 4684171ac6
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -970,7 +970,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
mshr.io.req.bits.offset := r_cpu_req_idx(offsetmsb,0) mshr.io.req.bits.offset := r_cpu_req_idx(offsetmsb,0)
mshr.io.req.bits.cmd := r_cpu_req_cmd mshr.io.req.bits.cmd := r_cpu_req_cmd
mshr.io.req.bits.typ := r_cpu_req_type mshr.io.req.bits.typ := r_cpu_req_type
mshr.io.req.bits.way_oh := Mux(tag_match, tag_match_way_oh, replaced_way_oh) mshr.io.req.bits.way_oh := Mux(tag_match && !flusher.io.mshr_req.valid, tag_match_way_oh, replaced_way_oh)
mshr.io.req.bits.data := cpu_req_data mshr.io.req.bits.data := cpu_req_data
mshr.io.mem_rep <> io.mem.xact_rep mshr.io.mem_rep <> io.mem.xact_rep