Decouple BaseTile from HasTileLinkMasterPort

src/main/scala/groundtest/Coreplex.scala

@@ -25,7 +25,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
     })
   )}
 
-  tiles.foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.masterNode }
+  tiles.flatMap(_.dcacheOpt).foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.node }
 
   val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes))
   pbusRAM.node := pbus.toVariableWidthSlaves

src/main/scala/groundtest/Tile.scala

@@ -31,7 +31,6 @@ case object GroundTestTilesKey extends Field[Seq[GroundTestTileParams]]
 abstract class GroundTestTile(params: GroundTestTileParams)(implicit p: Parameters) extends BaseTile(params)(p) {
   val slave = None
   val dcacheOpt = params.dcache.map { dc => LazyModule(HellaCache(0, dc.nMSHRs == 0)) }
-  dcacheOpt.foreach { tileBus.node := _.node }
 
   override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this))
 }

src/main/scala/tile/BaseTile.scala

@@ -99,19 +99,16 @@ trait CanHaveInstructionTracePort extends Bundle with HasTileParameters {
 
 /** Base class for all Tiles that use TileLink */
 abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
-    with HasTileParameters
-    with HasTileLinkMasterPort {
+    with HasTileParameters {
   override lazy val module = new BaseTileModule(this, () => new BaseTileBundle(this))
 }
 
 class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
-    with HasTileLinkMasterPortBundle
     with HasExternallyDrivenTileConstants
     with CanHaveInstructionTracePort
 
 class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
-    with HasTileParameters
-    with HasTileLinkMasterPortModule {
+    with HasTileParameters {
   require(xLen == 32 || xLen == 64)
   require(paddrBits <= maxPAddrBits)
   require(resetVectorLen <= xLen)