riscv/rocket-chip
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Decouple BaseTile from HasTileLinkMasterPort

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This commit is contained in:
Andrew Waterman 2017-10-05 22:23:58 -07:00
parent 86a1953287
commit 4645b61fd3
3 changed files with 3 additions and 7 deletions
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2
src/main/scala/groundtest/Coreplex.scala
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@ -25,7 +25,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
}) })
)} )}
tiles.foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.masterNode } tiles.flatMap(_.dcacheOpt).foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.node }
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes)) val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes))
pbusRAM.node := pbus.toVariableWidthSlaves pbusRAM.node := pbus.toVariableWidthSlaves

1
src/main/scala/groundtest/Tile.scala
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@ -31,7 +31,6 @@ case object GroundTestTilesKey extends Field[Seq[GroundTestTileParams]]
abstract class GroundTestTile(params: GroundTestTileParams)(implicit p: Parameters) extends BaseTile(params)(p) { abstract class GroundTestTile(params: GroundTestTileParams)(implicit p: Parameters) extends BaseTile(params)(p) {
val slave = None val slave = None
val dcacheOpt = params.dcache.map { dc => LazyModule(HellaCache(0, dc.nMSHRs == 0)) } val dcacheOpt = params.dcache.map { dc => LazyModule(HellaCache(0, dc.nMSHRs == 0)) }
dcacheOpt.foreach { tileBus.node := _.node }
override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this)) override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this))
} }

7
src/main/scala/tile/BaseTile.scala
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@ -99,19 +99,16 @@ trait CanHaveInstructionTracePort extends Bundle with HasTileParameters {
/** Base class for all Tiles that use TileLink */ /** Base class for all Tiles that use TileLink */
abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
with HasTileParameters with HasTileParameters {
with HasTileLinkMasterPort {
override lazy val module = new BaseTileModule(this, () => new BaseTileBundle(this)) override lazy val module = new BaseTileModule(this, () => new BaseTileBundle(this))
} }
class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer) class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
with HasTileLinkMasterPortBundle
with HasExternallyDrivenTileConstants with HasExternallyDrivenTileConstants
with CanHaveInstructionTracePort with CanHaveInstructionTracePort
class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io) class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
with HasTileParameters with HasTileParameters {
with HasTileLinkMasterPortModule {
require(xLen == 32 || xLen == 64) require(xLen == 32 || xLen == 64)
require(paddrBits <= maxPAddrBits) require(paddrBits <= maxPAddrBits)
require(resetVectorLen <= xLen) require(resetVectorLen <= xLen)