Decouple BaseTile from HasTileLinkMasterPort

2017-10-05 22:23:58 -07:00
parent 86a1953287
commit 4645b61fd3
3 changed files with 3 additions and 7 deletions
--- a/src/main/scala/groundtest/Coreplex.scala
+++ b/src/main/scala/groundtest/Coreplex.scala
@ -25,7 +25,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
    })
  )}

-  tiles.foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.masterNode }
+  tiles.flatMap(_.dcacheOpt).foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.node }

  val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes))
  pbusRAM.node := pbus.toVariableWidthSlaves