torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding mode traps, and x's were cropping up in situations that are benign in HW.
This commit is contained in:
Andrew Waterman
parent
90cae54ac4
commit
4608660f6e
@ -95,9 +95,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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Mux(sel === A2_BTYPE, Cat(inst(31,27), inst(16,10)),
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Mux(sel === A2_JTYPE, inst(18,7),
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inst(21,10))))
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val msbs = Mux(sel === A2_LTYPE, inst(26,7),
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val msbs = Mux(sel === A2_ZERO, Bits(0),
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Mux(sel === A2_LTYPE, inst(26,7).toFix,
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Mux(sel === A2_JTYPE, inst(31,19).toFix,
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Mux(sel === A2_ITYPE, inst(21), inst(31)).toFix))
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Mux(sel === A2_ITYPE, inst(21), inst(31)).toFix)))
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Cat(msbs, lsbs).toFix
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}
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@ -214,7 +214,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
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val read_impl = Bits(2)
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val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
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val read_veccfg = Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl)
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val read_veccfg = if (conf.vec) Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl) else Bits(0)
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val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0)
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rdata := AVec[Bits](
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reg_status.toBits, reg_epc, reg_badvaddr, reg_ebase,
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@ -59,7 +59,7 @@ class FPUCtrlSigs extends Bundle
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val toint = Bool()
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val fastpipe = Bool()
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val fma = Bool()
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val store = Bool()
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val round = Bool()
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val rdfsr = Bool()
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val wrfsr = Bool()
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}
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@ -75,67 +75,67 @@ class FPUDecoder extends Component
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val Y = Bool(true)
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val X = Bool(false)
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val decoder = DecodeLogic(io.inst,
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List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X),
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Array(FLW -> List(FCMD_LOAD, Y,N,N,N,Y,N,N,N,N,N,N),
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FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N),
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FSW -> List(FCMD_STORE, N,N,Y,N,Y,N,Y,N,N,N,N),
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FSD -> List(FCMD_STORE, N,N,Y,N,N,N,Y,N,N,N,N),
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MXTF_S -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,N,N),
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MXTF_D -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N,N,N),
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FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N,N,N),
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FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N,N,N),
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FCVT_S_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,Y,Y,N,N,N,N,N),
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FCVT_D_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,N,N),
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MFTX_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,N,N),
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MFTX_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,N,N),
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FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,N,N),
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FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,N,N),
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FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,N,N),
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FCVT_LU_S-> List(FCMD_CVT_LU_FMT,N,Y,N,N,Y,N,Y,N,N,N,N),
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FCVT_W_D -> List(FCMD_CVT_W_FMT, N,Y,N,N,N,N,Y,N,N,N,N),
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FCVT_WU_D-> List(FCMD_CVT_WU_FMT,N,Y,N,N,N,N,Y,N,N,N,N),
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FCVT_L_D -> List(FCMD_CVT_L_FMT, N,Y,N,N,N,N,Y,N,N,N,N),
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FCVT_LU_D-> List(FCMD_CVT_LU_FMT,N,Y,N,N,N,N,Y,N,N,N,N),
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FCVT_S_D -> List(FCMD_CVT_FMT_D, Y,Y,N,N,Y,N,N,Y,N,N,N),
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FCVT_D_S -> List(FCMD_CVT_FMT_S, Y,Y,N,N,N,N,N,Y,N,N,N),
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FEQ_S -> List(FCMD_EQ, N,Y,Y,N,Y,N,Y,N,N,N,N),
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FLT_S -> List(FCMD_LT, N,Y,Y,N,Y,N,Y,N,N,N,N),
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FLE_S -> List(FCMD_LE, N,Y,Y,N,Y,N,Y,N,N,N,N),
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FEQ_D -> List(FCMD_EQ, N,Y,Y,N,N,N,Y,N,N,N,N),
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FLT_D -> List(FCMD_LT, N,Y,Y,N,N,N,Y,N,N,N,N),
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FLE_D -> List(FCMD_LE, N,Y,Y,N,N,N,Y,N,N,N,N),
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MTFSR -> List(FCMD_MTFSR, N,N,N,N,Y,N,Y,N,N,Y,Y),
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MFFSR -> List(FCMD_MFFSR, N,N,N,N,Y,N,Y,N,N,Y,N),
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FSGNJ_S -> List(FCMD_SGNJ, Y,Y,Y,N,Y,N,N,Y,N,N,N),
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FSGNJN_S -> List(FCMD_SGNJN, Y,Y,Y,N,Y,N,N,Y,N,N,N),
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FSGNJX_S -> List(FCMD_SGNJX, Y,Y,Y,N,Y,N,N,Y,N,N,N),
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FSGNJ_D -> List(FCMD_SGNJ, Y,Y,Y,N,N,N,N,Y,N,N,N),
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FSGNJN_D -> List(FCMD_SGNJN, Y,Y,Y,N,N,N,N,Y,N,N,N),
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FSGNJX_D -> List(FCMD_SGNJX, Y,Y,Y,N,N,N,N,Y,N,N,N),
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FMIN_S -> List(FCMD_MIN, Y,Y,Y,N,Y,N,Y,Y,N,N,N),
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FMAX_S -> List(FCMD_MAX, Y,Y,Y,N,Y,N,Y,Y,N,N,N),
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FMIN_D -> List(FCMD_MIN, Y,Y,Y,N,N,N,Y,Y,N,N,N),
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FMAX_D -> List(FCMD_MAX, Y,Y,Y,N,N,N,Y,Y,N,N,N),
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FADD_S -> List(FCMD_ADD, Y,Y,Y,N,Y,N,N,N,Y,N,N),
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FSUB_S -> List(FCMD_SUB, Y,Y,Y,N,Y,N,N,N,Y,N,N),
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FMUL_S -> List(FCMD_MUL, Y,Y,Y,N,Y,N,N,N,Y,N,N),
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FADD_D -> List(FCMD_ADD, Y,Y,Y,N,N,N,N,N,Y,N,N),
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FSUB_D -> List(FCMD_SUB, Y,Y,Y,N,N,N,N,N,Y,N,N),
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FMUL_D -> List(FCMD_MUL, Y,Y,Y,N,N,N,N,N,Y,N,N),
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FMADD_S -> List(FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,Y,N,N),
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FMSUB_S -> List(FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,Y,N,N),
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FNMADD_S -> List(FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,Y,N,N),
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FNMSUB_S -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,Y,N,N),
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FMADD_D -> List(FCMD_MADD, Y,Y,Y,Y,N,N,N,N,Y,N,N),
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FMSUB_D -> List(FCMD_MSUB, Y,Y,Y,Y,N,N,N,N,Y,N,N),
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FNMADD_D -> List(FCMD_NMADD, Y,Y,Y,Y,N,N,N,N,Y,N,N),
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FNMSUB_D -> List(FCMD_NMSUB, Y,Y,Y,Y,N,N,N,N,Y,N,N)
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List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X),
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Array(FLW -> List(FCMD_LOAD, Y,N,N,N,Y,N,N,N,N,N,N,N),
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FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N,N),
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FSW -> List(FCMD_STORE, N,N,Y,N,Y,N,Y,N,N,N,N,N),
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FSD -> List(FCMD_STORE, N,N,Y,N,N,N,Y,N,N,N,N,N),
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MXTF_S -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,Y,N,N),
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MXTF_D -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,Y,N,N),
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FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N,Y,N,N),
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FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N,Y,N,N),
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FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N,Y,N,N),
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FCVT_S_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,Y,Y,N,N,N,Y,N,N),
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FCVT_D_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,Y,N,N,N,Y,N,N),
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FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N,Y,N,N),
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FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N,Y,N,N),
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FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,Y,N,N),
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MFTX_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y,N,N),
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MFTX_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y,N,N),
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FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,Y,N,N),
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FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,Y,N,N),
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FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,Y,N,N),
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FCVT_LU_S-> List(FCMD_CVT_LU_FMT,N,Y,N,N,Y,N,Y,N,N,Y,N,N),
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FCVT_W_D -> List(FCMD_CVT_W_FMT, N,Y,N,N,N,N,Y,N,N,Y,N,N),
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FCVT_WU_D-> List(FCMD_CVT_WU_FMT,N,Y,N,N,N,N,Y,N,N,Y,N,N),
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FCVT_L_D -> List(FCMD_CVT_L_FMT, N,Y,N,N,N,N,Y,N,N,Y,N,N),
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FCVT_LU_D-> List(FCMD_CVT_LU_FMT,N,Y,N,N,N,N,Y,N,N,Y,N,N),
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FCVT_S_D -> List(FCMD_CVT_FMT_D, Y,Y,N,N,Y,N,N,Y,N,Y,N,N),
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FCVT_D_S -> List(FCMD_CVT_FMT_S, Y,Y,N,N,N,N,N,Y,N,Y,N,N),
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FEQ_S -> List(FCMD_EQ, N,Y,Y,N,Y,N,Y,N,N,Y,N,N),
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FLT_S -> List(FCMD_LT, N,Y,Y,N,Y,N,Y,N,N,Y,N,N),
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FLE_S -> List(FCMD_LE, N,Y,Y,N,Y,N,Y,N,N,Y,N,N),
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FEQ_D -> List(FCMD_EQ, N,Y,Y,N,N,N,Y,N,N,Y,N,N),
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FLT_D -> List(FCMD_LT, N,Y,Y,N,N,N,Y,N,N,Y,N,N),
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FLE_D -> List(FCMD_LE, N,Y,Y,N,N,N,Y,N,N,Y,N,N),
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MTFSR -> List(FCMD_MTFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,Y),
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MFFSR -> List(FCMD_MFFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,N),
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FSGNJ_S -> List(FCMD_SGNJ, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N),
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FSGNJN_S -> List(FCMD_SGNJN, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N),
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FSGNJX_S -> List(FCMD_SGNJX, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N),
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FSGNJ_D -> List(FCMD_SGNJ, Y,Y,Y,N,N,N,N,Y,N,Y,N,N),
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FSGNJN_D -> List(FCMD_SGNJN, Y,Y,Y,N,N,N,N,Y,N,Y,N,N),
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FSGNJX_D -> List(FCMD_SGNJX, Y,Y,Y,N,N,N,N,Y,N,Y,N,N),
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FMIN_S -> List(FCMD_MIN, Y,Y,Y,N,Y,N,Y,Y,N,Y,N,N),
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FMAX_S -> List(FCMD_MAX, Y,Y,Y,N,Y,N,Y,Y,N,Y,N,N),
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FMIN_D -> List(FCMD_MIN, Y,Y,Y,N,N,N,Y,Y,N,Y,N,N),
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FMAX_D -> List(FCMD_MAX, Y,Y,Y,N,N,N,Y,Y,N,Y,N,N),
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FADD_S -> List(FCMD_ADD, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N),
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FSUB_S -> List(FCMD_SUB, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N),
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FMUL_S -> List(FCMD_MUL, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N),
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FADD_D -> List(FCMD_ADD, Y,Y,Y,N,N,N,N,N,Y,Y,N,N),
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FSUB_D -> List(FCMD_SUB, Y,Y,Y,N,N,N,N,N,Y,Y,N,N),
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FMUL_D -> List(FCMD_MUL, Y,Y,Y,N,N,N,N,N,Y,Y,N,N),
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FMADD_S -> List(FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N),
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FMSUB_S -> List(FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N),
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FNMADD_S -> List(FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N),
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FNMSUB_S -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N),
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FMADD_D -> List(FCMD_MADD, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N),
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FMSUB_D -> List(FCMD_MSUB, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N),
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FNMADD_D -> List(FCMD_NMADD, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N),
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FNMSUB_D -> List(FCMD_NMSUB, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N)
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))
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val cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: rdfsr :: wrfsr :: Nil = decoder
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val cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: round :: rdfsr :: wrfsr :: Nil = decoder
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io.sigs.cmd := cmd
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io.sigs.wen := wen.toBool
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@ -147,6 +147,7 @@ class FPUDecoder extends Component
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io.sigs.toint := toint.toBool
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io.sigs.fastpipe := fastpipe.toBool
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io.sigs.fma := fma.toBool
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io.sigs.round := round.toBool
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io.sigs.rdfsr := rdfsr.toBool
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io.sigs.wrfsr := wrfsr.toBool
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}
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@ -614,5 +615,5 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Component
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io.ctrl.sboard_clr := wen(0) && useScoreboard(x => wsrc === UFix(x._2))
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io.ctrl.sboard_clra := waddr
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// we don't currently support round-max-magnitude (rm=4)
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io.ctrl.illegal_rm := ex_rm(2)
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io.ctrl.illegal_rm := ex_rm(2) && ctrl.round
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}
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@ -593,7 +593,6 @@ class DataArray(implicit conf: DCacheConfig) extends Component {
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val resp = Vec(conf.ways){ Bits(OUTPUT, MEM_DATA_BITS) }
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}
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val wmask = FillInterleaved(conf.databits, io.write.bits.wmask)
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val waddr = io.write.bits.addr >> conf.ramoffbits
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val raddr = io.read.bits.addr >> conf.ramoffbits
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@ -624,6 +623,7 @@ class DataArray(implicit conf: DCacheConfig) extends Component {
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}
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}
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} else {
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val wmask = FillInterleaved(conf.databits, io.write.bits.wmask)
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for (w <- 0 until conf.ways) {
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val rdata = Reg() { Bits() }
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val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=MEM_DATA_BITS) }
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@ -837,8 +837,8 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
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val s1_writeback = s1_clk_en && !s1_valid && !s1_replay
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val s2_tag_match_way = RegEn(s1_tag_match_way, s1_clk_en)
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val s2_tag_match = s2_tag_match_way.orR
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val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEn(meta.io.resp(w).state, s1_clk_en && s1_tag_eq_way(w))){Bits()})
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val s2_hit = conf.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === conf.co.newStateOnHit(s2_req.cmd, s2_hit_state)
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val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEn(meta.io.resp(w).state, s1_clk_en)){Bits()})
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val s2_hit = s2_tag_match && conf.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === conf.co.newStateOnHit(s2_req.cmd, s2_hit_state)
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val s2_data = Vec(conf.ways){Bits(width = MEM_DATA_BITS)}
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for (w <- 0 until conf.ways) {
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@ -921,7 +921,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
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wb.io.req <> mshr.io.wb_req
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wb.io.meta_read <> metaReadArb.io.in(2)
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wb.io.data_req <> readArb.io.in(1)
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wb.io.data_resp <> data_resp_mux
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wb.io.data_resp := data_resp_mux
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wb.io.probe_rep_data <> io.mem.probe_rep_data
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// store->load bypassing
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