diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 0303b552..3ceca7e8 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -95,9 +95,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component Mux(sel === A2_BTYPE, Cat(inst(31,27), inst(16,10)), Mux(sel === A2_JTYPE, inst(18,7), inst(21,10)))) - val msbs = Mux(sel === A2_LTYPE, inst(26,7), + val msbs = Mux(sel === A2_ZERO, Bits(0), + Mux(sel === A2_LTYPE, inst(26,7).toFix, Mux(sel === A2_JTYPE, inst(31,19).toFix, - Mux(sel === A2_ITYPE, inst(21), inst(31)).toFix)) + Mux(sel === A2_ITYPE, inst(21), inst(31)).toFix))) Cat(msbs, lsbs).toFix } diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 38b64bb1..5c36034c 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -214,7 +214,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component val read_impl = Bits(2) val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS - val read_veccfg = Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl) + val read_veccfg = if (conf.vec) Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl) else Bits(0) val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0) rdata := AVec[Bits]( reg_status.toBits, reg_epc, reg_badvaddr, reg_ebase, diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index 7cd5b989..ef6d708c 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -59,7 +59,7 @@ class FPUCtrlSigs extends Bundle val toint = Bool() val fastpipe = Bool() val fma = Bool() - val store = Bool() + val round = Bool() val rdfsr = Bool() val wrfsr = Bool() } @@ -75,67 +75,67 @@ class FPUDecoder extends Component val Y = Bool(true) val X = Bool(false) val decoder = DecodeLogic(io.inst, - List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X), - Array(FLW -> List(FCMD_LOAD, Y,N,N,N,Y,N,N,N,N,N,N), - FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N), - FSW -> List(FCMD_STORE, N,N,Y,N,Y,N,Y,N,N,N,N), - FSD -> List(FCMD_STORE, N,N,Y,N,N,N,Y,N,N,N,N), - MXTF_S -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,N,N), - MXTF_D -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,N,N), - FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N,N,N), - FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N,N,N), - FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N,N,N), - FCVT_S_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,Y,Y,N,N,N,N,N), - FCVT_D_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,Y,N,N,N,N,N), - FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N,N,N), - FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N,N,N), - FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,N,N), - MFTX_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,N,N), - MFTX_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,N,N), - FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,N,N), - FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,N,N), - FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,N,N), - FCVT_LU_S-> List(FCMD_CVT_LU_FMT,N,Y,N,N,Y,N,Y,N,N,N,N), - FCVT_W_D -> List(FCMD_CVT_W_FMT, N,Y,N,N,N,N,Y,N,N,N,N), - FCVT_WU_D-> List(FCMD_CVT_WU_FMT,N,Y,N,N,N,N,Y,N,N,N,N), - FCVT_L_D -> List(FCMD_CVT_L_FMT, N,Y,N,N,N,N,Y,N,N,N,N), - FCVT_LU_D-> List(FCMD_CVT_LU_FMT,N,Y,N,N,N,N,Y,N,N,N,N), - FCVT_S_D -> List(FCMD_CVT_FMT_D, Y,Y,N,N,Y,N,N,Y,N,N,N), - FCVT_D_S -> List(FCMD_CVT_FMT_S, Y,Y,N,N,N,N,N,Y,N,N,N), - FEQ_S -> List(FCMD_EQ, N,Y,Y,N,Y,N,Y,N,N,N,N), - FLT_S -> List(FCMD_LT, N,Y,Y,N,Y,N,Y,N,N,N,N), - FLE_S -> List(FCMD_LE, N,Y,Y,N,Y,N,Y,N,N,N,N), - FEQ_D -> List(FCMD_EQ, N,Y,Y,N,N,N,Y,N,N,N,N), - FLT_D -> List(FCMD_LT, N,Y,Y,N,N,N,Y,N,N,N,N), - FLE_D -> List(FCMD_LE, N,Y,Y,N,N,N,Y,N,N,N,N), - MTFSR -> List(FCMD_MTFSR, N,N,N,N,Y,N,Y,N,N,Y,Y), - MFFSR -> List(FCMD_MFFSR, N,N,N,N,Y,N,Y,N,N,Y,N), - FSGNJ_S -> List(FCMD_SGNJ, Y,Y,Y,N,Y,N,N,Y,N,N,N), - FSGNJN_S -> List(FCMD_SGNJN, Y,Y,Y,N,Y,N,N,Y,N,N,N), - FSGNJX_S -> List(FCMD_SGNJX, Y,Y,Y,N,Y,N,N,Y,N,N,N), - FSGNJ_D -> List(FCMD_SGNJ, Y,Y,Y,N,N,N,N,Y,N,N,N), - FSGNJN_D -> List(FCMD_SGNJN, Y,Y,Y,N,N,N,N,Y,N,N,N), - FSGNJX_D -> List(FCMD_SGNJX, Y,Y,Y,N,N,N,N,Y,N,N,N), - FMIN_S -> List(FCMD_MIN, Y,Y,Y,N,Y,N,Y,Y,N,N,N), - FMAX_S -> List(FCMD_MAX, Y,Y,Y,N,Y,N,Y,Y,N,N,N), - FMIN_D -> List(FCMD_MIN, Y,Y,Y,N,N,N,Y,Y,N,N,N), - FMAX_D -> List(FCMD_MAX, Y,Y,Y,N,N,N,Y,Y,N,N,N), - FADD_S -> List(FCMD_ADD, Y,Y,Y,N,Y,N,N,N,Y,N,N), - FSUB_S -> List(FCMD_SUB, Y,Y,Y,N,Y,N,N,N,Y,N,N), - FMUL_S -> List(FCMD_MUL, Y,Y,Y,N,Y,N,N,N,Y,N,N), - FADD_D -> List(FCMD_ADD, Y,Y,Y,N,N,N,N,N,Y,N,N), - FSUB_D -> List(FCMD_SUB, Y,Y,Y,N,N,N,N,N,Y,N,N), - FMUL_D -> List(FCMD_MUL, Y,Y,Y,N,N,N,N,N,Y,N,N), - FMADD_S -> List(FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,Y,N,N), - FMSUB_S -> List(FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,Y,N,N), - FNMADD_S -> List(FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,Y,N,N), - FNMSUB_S -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,Y,N,N), - FMADD_D -> List(FCMD_MADD, Y,Y,Y,Y,N,N,N,N,Y,N,N), - FMSUB_D -> List(FCMD_MSUB, Y,Y,Y,Y,N,N,N,N,Y,N,N), - FNMADD_D -> List(FCMD_NMADD, Y,Y,Y,Y,N,N,N,N,Y,N,N), - FNMSUB_D -> List(FCMD_NMSUB, Y,Y,Y,Y,N,N,N,N,Y,N,N) + List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X), + Array(FLW -> List(FCMD_LOAD, Y,N,N,N,Y,N,N,N,N,N,N,N), + FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N,N), + FSW -> List(FCMD_STORE, N,N,Y,N,Y,N,Y,N,N,N,N,N), + FSD -> List(FCMD_STORE, N,N,Y,N,N,N,Y,N,N,N,N,N), + MXTF_S -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,Y,N,N), + MXTF_D -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,Y,N,N), + FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N,Y,N,N), + FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N,Y,N,N), + FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N,Y,N,N), + FCVT_S_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,Y,Y,N,N,N,Y,N,N), + FCVT_D_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,Y,N,N,N,Y,N,N), + FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N,Y,N,N), + FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N,Y,N,N), + FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,Y,N,N), + MFTX_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y,N,N), + MFTX_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y,N,N), + FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,Y,N,N), + FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,Y,N,N), + FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,Y,N,N), + FCVT_LU_S-> List(FCMD_CVT_LU_FMT,N,Y,N,N,Y,N,Y,N,N,Y,N,N), + FCVT_W_D -> List(FCMD_CVT_W_FMT, N,Y,N,N,N,N,Y,N,N,Y,N,N), + FCVT_WU_D-> List(FCMD_CVT_WU_FMT,N,Y,N,N,N,N,Y,N,N,Y,N,N), + FCVT_L_D -> List(FCMD_CVT_L_FMT, N,Y,N,N,N,N,Y,N,N,Y,N,N), + FCVT_LU_D-> List(FCMD_CVT_LU_FMT,N,Y,N,N,N,N,Y,N,N,Y,N,N), + FCVT_S_D -> List(FCMD_CVT_FMT_D, Y,Y,N,N,Y,N,N,Y,N,Y,N,N), + FCVT_D_S -> List(FCMD_CVT_FMT_S, Y,Y,N,N,N,N,N,Y,N,Y,N,N), + FEQ_S -> List(FCMD_EQ, N,Y,Y,N,Y,N,Y,N,N,Y,N,N), + FLT_S -> List(FCMD_LT, N,Y,Y,N,Y,N,Y,N,N,Y,N,N), + FLE_S -> List(FCMD_LE, N,Y,Y,N,Y,N,Y,N,N,Y,N,N), + FEQ_D -> List(FCMD_EQ, N,Y,Y,N,N,N,Y,N,N,Y,N,N), + FLT_D -> List(FCMD_LT, N,Y,Y,N,N,N,Y,N,N,Y,N,N), + FLE_D -> List(FCMD_LE, N,Y,Y,N,N,N,Y,N,N,Y,N,N), + MTFSR -> List(FCMD_MTFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,Y), + MFFSR -> List(FCMD_MFFSR, N,N,N,N,Y,N,Y,N,N,Y,Y,N), + FSGNJ_S -> List(FCMD_SGNJ, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), + FSGNJN_S -> List(FCMD_SGNJN, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), + FSGNJX_S -> List(FCMD_SGNJX, Y,Y,Y,N,Y,N,N,Y,N,Y,N,N), + FSGNJ_D -> List(FCMD_SGNJ, Y,Y,Y,N,N,N,N,Y,N,Y,N,N), + FSGNJN_D -> List(FCMD_SGNJN, Y,Y,Y,N,N,N,N,Y,N,Y,N,N), + FSGNJX_D -> List(FCMD_SGNJX, Y,Y,Y,N,N,N,N,Y,N,Y,N,N), + FMIN_S -> List(FCMD_MIN, Y,Y,Y,N,Y,N,Y,Y,N,Y,N,N), + FMAX_S -> List(FCMD_MAX, Y,Y,Y,N,Y,N,Y,Y,N,Y,N,N), + FMIN_D -> List(FCMD_MIN, Y,Y,Y,N,N,N,Y,Y,N,Y,N,N), + FMAX_D -> List(FCMD_MAX, Y,Y,Y,N,N,N,Y,Y,N,Y,N,N), + FADD_S -> List(FCMD_ADD, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N), + FSUB_S -> List(FCMD_SUB, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N), + FMUL_S -> List(FCMD_MUL, Y,Y,Y,N,Y,N,N,N,Y,Y,N,N), + FADD_D -> List(FCMD_ADD, Y,Y,Y,N,N,N,N,N,Y,Y,N,N), + FSUB_D -> List(FCMD_SUB, Y,Y,Y,N,N,N,N,N,Y,Y,N,N), + FMUL_D -> List(FCMD_MUL, Y,Y,Y,N,N,N,N,N,Y,Y,N,N), + FMADD_S -> List(FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), + FMSUB_S -> List(FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), + FNMADD_S -> List(FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), + FNMSUB_S -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,Y,Y,N,N), + FMADD_D -> List(FCMD_MADD, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N), + FMSUB_D -> List(FCMD_MSUB, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N), + FNMADD_D -> List(FCMD_NMADD, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N), + FNMSUB_D -> List(FCMD_NMSUB, Y,Y,Y,Y,N,N,N,N,Y,Y,N,N) )) - val cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: rdfsr :: wrfsr :: Nil = decoder + val cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: round :: rdfsr :: wrfsr :: Nil = decoder io.sigs.cmd := cmd io.sigs.wen := wen.toBool @@ -147,6 +147,7 @@ class FPUDecoder extends Component io.sigs.toint := toint.toBool io.sigs.fastpipe := fastpipe.toBool io.sigs.fma := fma.toBool + io.sigs.round := round.toBool io.sigs.rdfsr := rdfsr.toBool io.sigs.wrfsr := wrfsr.toBool } @@ -614,5 +615,5 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Component io.ctrl.sboard_clr := wen(0) && useScoreboard(x => wsrc === UFix(x._2)) io.ctrl.sboard_clra := waddr // we don't currently support round-max-magnitude (rm=4) - io.ctrl.illegal_rm := ex_rm(2) + io.ctrl.illegal_rm := ex_rm(2) && ctrl.round } diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 525d271e..a98202cf 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -593,7 +593,6 @@ class DataArray(implicit conf: DCacheConfig) extends Component { val resp = Vec(conf.ways){ Bits(OUTPUT, MEM_DATA_BITS) } } - val wmask = FillInterleaved(conf.databits, io.write.bits.wmask) val waddr = io.write.bits.addr >> conf.ramoffbits val raddr = io.read.bits.addr >> conf.ramoffbits @@ -624,6 +623,7 @@ class DataArray(implicit conf: DCacheConfig) extends Component { } } } else { + val wmask = FillInterleaved(conf.databits, io.write.bits.wmask) for (w <- 0 until conf.ways) { val rdata = Reg() { Bits() } val array = Mem(conf.sets*REFILL_CYCLES, seqRead = true){ Bits(width=MEM_DATA_BITS) } @@ -837,8 +837,8 @@ class HellaCache(implicit conf: DCacheConfig) extends Component { val s1_writeback = s1_clk_en && !s1_valid && !s1_replay val s2_tag_match_way = RegEn(s1_tag_match_way, s1_clk_en) val s2_tag_match = s2_tag_match_way.orR - val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEn(meta.io.resp(w).state, s1_clk_en && s1_tag_eq_way(w))){Bits()}) - val s2_hit = conf.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === conf.co.newStateOnHit(s2_req.cmd, s2_hit_state) + val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEn(meta.io.resp(w).state, s1_clk_en)){Bits()}) + val s2_hit = s2_tag_match && conf.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === conf.co.newStateOnHit(s2_req.cmd, s2_hit_state) val s2_data = Vec(conf.ways){Bits(width = MEM_DATA_BITS)} for (w <- 0 until conf.ways) { @@ -921,7 +921,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component { wb.io.req <> mshr.io.wb_req wb.io.meta_read <> metaReadArb.io.in(2) wb.io.data_req <> readArb.io.in(1) - wb.io.data_resp <> data_resp_mux + wb.io.data_resp := data_resp_mux wb.io.probe_rep_data <> io.mem.probe_rep_data // store->load bypassing