riscv/rocket-chip
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torture revealed a couple bugs

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FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
This commit is contained in:
Andrew Waterman
2012-12-04 05:57:53 -08:00
parent 90cae54ac4
commit 4608660f6e
4 changed files with 71 additions and 69 deletions
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2
rocket/src/main/scala/dpath_util.scala
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@ -214,7 +214,7 @@ class PCR(implicit conf: RocketConfiguration) extends Component
val read_impl = Bits(2)
val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
val read_veccfg = Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl)
val read_veccfg = if (conf.vec) Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl) else Bits(0)
val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0)
rdata := AVec[Bits](
reg_status.toBits, reg_epc, reg_badvaddr, reg_ebase,