riscv/rocket-chip
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torture revealed a couple bugs

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FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
This commit is contained in:
Andrew Waterman
2012-12-04 05:57:53 -08:00
parent 90cae54ac4
commit 4608660f6e
4 changed files with 71 additions and 69 deletions
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5
rocket/src/main/scala/dpath.scala
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@ -95,9 +95,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
Mux(sel === A2_BTYPE, Cat(inst(31,27), inst(16,10)),
Mux(sel === A2_JTYPE, inst(18,7),
inst(21,10))))
val msbs = Mux(sel === A2_LTYPE, inst(26,7),
val msbs = Mux(sel === A2_ZERO, Bits(0),
Mux(sel === A2_LTYPE, inst(26,7).toFix,
Mux(sel === A2_JTYPE, inst(31,19).toFix,
Mux(sel === A2_ITYPE, inst(21), inst(31)).toFix))
Mux(sel === A2_ITYPE, inst(21), inst(31)).toFix)))
Cat(msbs, lsbs).toFix
}