riscv/rocket-chip
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Fix bug in D$ AMO/storegen logic

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This commit is contained in:
Andrew Waterman 2016-05-24 16:26:07 -07:00
parent 5dac7b818d
commit 4605b616c1
1 changed files with 3 additions and 3 deletions
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6
rocket/src/main/scala/dcache.scala
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@ -387,9 +387,9 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
// AMOs // AMOs
if (usingAtomics) { if (usingAtomics) {
val amoalu = Module(new AMOALU) val amoalu = Module(new AMOALU)
amoalu.io.addr := s2_req.addr amoalu.io.addr := pstore1_addr
amoalu.io.cmd := s2_req.cmd amoalu.io.cmd := pstore1_cmd
amoalu.io.typ := s2_req.typ amoalu.io.typ := pstore1_typ
amoalu.io.lhs := s2_data_word amoalu.io.lhs := s2_data_word
amoalu.io.rhs := pstore1_data amoalu.io.rhs := pstore1_data
pstore1_storegen_data := amoalu.io.out pstore1_storegen_data := amoalu.io.out