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tilelink2: include Operation constructors

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This commit is contained in:
Wesley W. Terpstra
2016-08-19 20:28:58 -07:00
parent 5b10c1a328
commit 45e152e97e
2 changed files with 335 additions and 29 deletions
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13
uncore/src/main/scala/tilelink2/Parameters.scala
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@ -36,7 +36,7 @@ case class IdRange(start: Int, end: Int)
def shift(x: Int) = IdRange(start+x, end+x)
}
// An potentially empty inclusive range of 2-powers [min, max]
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
@ -269,10 +269,19 @@ case class TLEdgeParameters(
client: TLClientPortParameters,
manager: TLManagerPortParameters)
{
val maxTransfer = max(client.maxTransfer, manager.maxTransfer)
val maxLgSize = log2Up(maxTransfer)
val bundle = TLBundleParameters(
addressBits = log2Up(manager.maxAddress + 1) - log2Up(manager.beatBytes),
dataBits = manager.beatBytes * 8,
sourceBits = log2Up(client.endSourceId),
sinkBits = log2Up(manager.endSinkId),
sizeBits = log2Up(log2Up(max(client.maxTransfer, manager.maxTransfer))+1))
sizeBits = log2Up(maxLgSize+1))
def addressMask(lgSize: UInt) = Vec.tabulate(maxLgSize) { UInt(_) < lgSize } .toBits.asUInt
def isAligned(address: UInt, lgSize: UInt) = (address & addressMask(lgSize)) === UInt(0)
// !!! wrong:
def fullMask(address: UInt, lgSize: UInt) = UInt(0)
}