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ahb: ignore hrdata on an AHB error

From the AHB spec:
 "A slave only has to provide valid data when a transfer completes with an OKAY
  response. ERROR responses do not require valid read data."
This commit is contained in:
Wesley W. Terpstra
2017-10-30 18:07:25 -07:00
parent 6318d7d44c
commit 45a904b396
3 changed files with 14 additions and 4 deletions

View File

@ -49,7 +49,7 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
{
val node = AHBIdentityNode()
val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr)))
val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
val model = LazyModule(new TLRAMModel("AHBFuzzMaster", ignoreErrorData=true))
(node
:= TLToAHB(aFlow)

View File

@ -106,7 +106,14 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
out.a.bits.mask := MaskGen(d_addr, d_size, beatBytes)
out.d.ready := d_recv // backpressure AccessAckData arriving faster than AHB beats
in.hrdata := out.d.bits.data
// NOTE: on error, we present the read result on the hreadyout LOW cycle
// This means that if you latch hrdata from an error, the result is garbage.
// To fix this would require a bus-wide register, and the AHB spec says this:
// "A slave only has to provide valid data when a transfer completes with an OKAY
// response. ERROR responses do not require valid read data."
// Therefore, we choose to accept this slight TL-AHB infidelity.
in.hrdata := out.d.bits.data
// In a perfect world, we'd use these signals
val hresp = d_error || (out.d.valid && out.d.bits.error)