ahb: ignore hrdata on an AHB error
From the AHB spec: "A slave only has to provide valid data when a transfer completes with an OKAY response. ERROR responses do not require valid read data."
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@ -49,7 +49,7 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
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{
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val node = AHBIdentityNode()
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val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr)))
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val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
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val model = LazyModule(new TLRAMModel("AHBFuzzMaster", ignoreErrorData=true))
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(node
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:= TLToAHB(aFlow)
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@ -106,7 +106,14 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
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out.a.bits.mask := MaskGen(d_addr, d_size, beatBytes)
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out.d.ready := d_recv // backpressure AccessAckData arriving faster than AHB beats
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in.hrdata := out.d.bits.data
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// NOTE: on error, we present the read result on the hreadyout LOW cycle
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// This means that if you latch hrdata from an error, the result is garbage.
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// To fix this would require a bus-wide register, and the AHB spec says this:
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// "A slave only has to provide valid data when a transfer completes with an OKAY
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// response. ERROR responses do not require valid read data."
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// Therefore, we choose to accept this slight TL-AHB infidelity.
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in.hrdata := out.d.bits.data
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// In a perfect world, we'd use these signals
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val hresp = d_error || (out.d.valid && out.d.bits.error)
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