45a904b396
From the AHB spec: "A slave only has to provide valid data when a transfer completes with an OKAY response. ERROR responses do not require valid read data."
103 lines
3.3 KiB
Scala
103 lines
3.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.ahb
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.devices.tilelink.TLTestRAM
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.unittest._
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class RRTest0(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter(address, 0, 32, 0, 4)(
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new AHBRegBundle((), _) with RRTest0Bundle)(
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new AHBRegModule((), _, _) with RRTest0Module)
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class RRTest1(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter(address, 0, 32, 1, 4, false)(
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new AHBRegBundle((), _) with RRTest1Bundle)(
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new AHBRegModule((), _, _) with RRTest1Module)
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class AHBFuzzNative(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
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{
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val fuzz = LazyModule(new TLFuzzer(txns))
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val model = LazyModule(new TLRAMModel("AHBFuzzNative"))
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val xbar = LazyModule(new AHBFanout)
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val ram = LazyModule(new AHBRAM(AddressSet(0x0, 0xff)))
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val gpio = LazyModule(new RRTest0(0x100))
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xbar.node := TLToAHB(aFlow) := TLDelayer(0.1) := model.node := fuzz.node
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ram.node := xbar.node
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gpio.node := xbar.node
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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}
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}
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class AHBNativeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut = Module(LazyModule(new AHBFuzzNative(aFlow, txns)).module)
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io.finished := dut.io.finished
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}
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trait HasFuzzTarget {
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val fuzzAddr = AddressSet(0x0, 0xfff)
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val pattern = Seq(AddressSet(0x8, ~0x808), // ie: 0x8-0xf, 0x18-0x1f, ... 0x7f8-0x7ff
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AddressSet(0x900, ~0x900)) // ie: 0x900-0x9ff, 0xb00-0xbff, ... 0xf00-0xfff
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}
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class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule with HasFuzzTarget
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{
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val node = AHBIdentityNode()
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val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr)))
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val model = LazyModule(new TLRAMModel("AHBFuzzMaster", ignoreErrorData=true))
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(node
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:= TLToAHB(aFlow)
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:= TLDelayer(0.2)
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:= TLBuffer(BufferParams.flow)
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:= TLDelayer(0.2)
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:= TLErrorEvaluator(pattern, testOn=true, testOff=true)
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:= model.node
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:= fuzz.node)
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val finished = Bool(OUTPUT)
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})
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io.finished := fuzz.module.io.finished
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}
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}
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class AHBFuzzSlave()(implicit p: Parameters) extends SimpleLazyModule with HasFuzzTarget
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{
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val node = AHBIdentityNode()
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val ram = LazyModule(new TLTestRAM(fuzzAddr))
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(ram.node
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:= TLErrorEvaluator(pattern)
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:= TLFragmenter(4, 16)
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:= TLDelayer(0.2)
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:= TLBuffer(BufferParams.flow)
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:= TLDelayer(0.2)
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:= AHBToTL()
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:= node)
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}
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class AHBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
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{
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val master = LazyModule(new AHBFuzzMaster(aFlow, txns))
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val slave = LazyModule(new AHBFuzzSlave)
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slave.node := master.node
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := master.module.io.finished
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}
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}
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class AHBBridgeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val dut = Module(LazyModule(new AHBFuzzBridge(aFlow, txns)).module)
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io.finished := dut.io.finished
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}
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