Use a generic UInt for TileLink op sizes, rather than MT_xx enum
This commit is contained in:
parent
a857b08c59
commit
458520c8f6
@ -82,7 +82,7 @@ class ComparatorSource(implicit val p: Parameters) extends Module
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val raw_operand_size = NoiseMaker(2, inc) | UInt(0, M_SZ)
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val max_operand_size = UInt(log2Up(tlDataBytes))
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val get_operand_size = Mux(raw_operand_size > max_operand_size, max_operand_size, raw_operand_size)
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val atomic_operand_size = Mux(NoiseMaker(1, inc)(0), MT_W, MT_D)
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val atomic_operand_size = UInt(2) + NoiseMaker(1, inc) // word or dword
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// Generate random, but valid addr_bytes
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val raw_addr_byte = NoiseMaker(tlByteAddrBits, inc)
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@ -26,8 +26,8 @@ trait HasGeneratorParameters extends HasGroundTestParameters {
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val genWordBits = 32
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val genWordBytes = genWordBits / 8
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val wordOffset = log2Up(genWordBytes)
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val wordSize = MT_WU
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val wordOffset = log2Ceil(genWordBytes)
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val wordSize = UInt(log2Ceil(genWordBytes))
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require(startAddress % BigInt(genWordBytes) == 0)
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}
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@ -25,7 +25,7 @@ abstract class Regression(implicit val p: Parameters)
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def disableCache() {
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io.cache.req.valid := Bool(false)
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io.cache.req.bits.addr := UInt(memStart)
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io.cache.req.bits.typ := MT_D
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io.cache.req.bits.typ := UInt(0)
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io.cache.req.bits.cmd := M_XRD
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io.cache.req.bits.tag := UInt(0)
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io.cache.req.bits.data := Bits(0)
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@ -71,7 +71,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
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io.cache.req.valid := !get_sent && started
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io.cache.req.bits.addr := UInt(addrMap("io:int:bootrom").start)
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io.cache.req.bits.typ := MT_W
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io.cache.req.bits.typ := UInt(log2Ceil(32 / 8))
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io.cache.req.bits.cmd := M_XRD
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io.cache.req.bits.tag := UInt(0)
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io.cache.invalidate_lr := Bool(false)
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@ -493,7 +493,7 @@ class ReleaseRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := sending && (state === s_write || state === s_read)
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io.cache.req.bits.addr := Cat(addr_blocks(req_idx), UInt(0, blockOffset))
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io.cache.req.bits.typ := MT_D
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io.cache.req.bits.typ := UInt(log2Ceil(64 / 8))
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io.cache.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
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io.cache.req.bits.tag := UInt(0)
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io.cache.req.bits.data := data(req_idx)
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@ -624,7 +624,7 @@ class MergedPutRegression(implicit p: Parameters) extends Regression()(p)
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io.cache.req.valid := (state === s_cache_req)
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io.cache.req.bits.cmd := M_XWR
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io.cache.req.bits.typ := MT_D
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io.cache.req.bits.typ := UInt(log2Ceil(64 / 8))
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io.cache.req.bits.addr := UInt(memStart)
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io.cache.req.bits.data := UInt(1)
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io.cache.req.bits.tag := UInt(0)
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@ -718,7 +718,7 @@ class RegressionTest(implicit p: Parameters) extends GroundTest()(p) {
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io.mem.head.grant.ready := Bool(false)
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io.cache.head.req.valid := Bool(false)
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io.cache.head.req.bits.addr := UInt(0)
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io.cache.head.req.bits.typ := MT_D
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io.cache.head.req.bits.typ := UInt(log2Ceil(64 / 8))
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io.cache.head.req.bits.cmd := M_XRD
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io.cache.head.req.bits.tag := UInt(0)
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io.cache.head.req.bits.phys := Bool(true)
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@ -481,7 +481,7 @@ class TraceGenerator(id: Int)
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io.mem.req.valid := reqValid
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io.mem.req.bits.addr := reqAddr
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io.mem.req.bits.data := reqData
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io.mem.req.bits.typ := MT_D
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io.mem.req.bits.typ := UInt(log2Ceil(numBytesInWord))
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io.mem.req.bits.cmd := reqCmd
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io.mem.req.bits.tag := reqTag
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@ -1 +1 @@
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Subproject commit 65da94f84a2ba5a61a8bcf3ebdd8ca57f6d899ca
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Subproject commit d34419ff39072d999371641da520cdce687fd21c
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@ -7,6 +7,18 @@ import Chisel._
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import scala.math._
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trait ScalarOpConstants {
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val MT_SZ = 3
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val MT_X = BitPat("b???")
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val MT_B = UInt("b000")
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val MT_H = UInt("b001")
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val MT_W = UInt("b010")
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val MT_D = UInt("b011")
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val MT_BU = UInt("b100")
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val MT_HU = UInt("b101")
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val MT_WU = UInt("b110")
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def mtSize(mt: UInt) = mt(MT_SZ-2, 0)
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def mtSigned(mt: UInt) = !mt(MT_SZ-1)
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val SZ_BR = 3
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val BR_X = BitPat("b???")
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val BR_EQ = UInt(0, 3)
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@ -397,7 +397,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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// load data subword mux/sign extension
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val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes))
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val s2_data_word = s2_data >> Cat(s2_word_idx, UInt(0, log2Up(coreDataBits)))
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val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc, wordBytes)
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val loadgen = new LoadGen(s2_req.typ, mtSigned(s2_req.typ), s2_req.addr, s2_data_word, s2_sc, wordBytes)
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io.cpu.resp.bits.data := loadgen.data | s2_sc_fail
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io.cpu.resp.bits.data_word_bypass := loadgen.wordData
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io.cpu.resp.bits.store_data := pstore1_data
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@ -443,7 +443,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) {
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// load response
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val load_wb = Reg(next=io.dmem_resp_val)
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val load_wb_single = RegEnable(io.dmem_resp_type === MT_W || io.dmem_resp_type === MT_WU, io.dmem_resp_val)
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val load_wb_single = RegEnable(!io.dmem_resp_type(0), io.dmem_resp_val)
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val load_wb_data = RegEnable(io.dmem_resp_data, io.dmem_resp_val)
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val load_wb_tag = RegEnable(io.dmem_resp_tag, io.dmem_resp_val)
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val rec_s = hardfloat.recFNFromFN(8, 24, load_wb_data)
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@ -187,7 +187,7 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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fq.io.deq.ready := io.finish.ready && (state === s_finish)
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val storegen = new StoreGen(req.typ, req.addr, req.data, wordBytes)
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val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc, wordBytes)
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val loadgen = new LoadGen(req.typ, mtSigned(req.typ), req.addr, grant_word, req_cmd_sc, wordBytes)
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val beat_mask = (storegen.mask << Cat(beatOffset(req.addr), UInt(0, wordOffBits)))
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val beat_data = Fill(beatWords, storegen.data)
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@ -1062,7 +1062,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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// load data subword mux/sign extension
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val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(coreDataBits)))
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val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
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val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc, wordBytes)
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val loadgen = new LoadGen(s2_req.typ, mtSigned(s2_req.typ), s2_req.addr, s2_data_word, s2_sc, wordBytes)
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amoalu.io.addr := s2_req.addr
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amoalu.io.cmd := s2_req.cmd
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@ -7,17 +7,6 @@ import Chisel._
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object MemoryOpConstants extends MemoryOpConstants
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trait MemoryOpConstants {
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val MT_SZ = 3
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val MT_X = BitPat("b???")
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val MT_B = UInt("b000")
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val MT_H = UInt("b001")
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val MT_W = UInt("b010")
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val MT_D = UInt("b011")
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val MT_BU = UInt("b100")
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val MT_HU = UInt("b101")
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val MT_WU = UInt("b110")
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val MT_Q = UInt("b111")
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val NUM_XA_OPS = 9
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val M_SZ = 5
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val M_X = BitPat("b?????");
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@ -73,16 +73,6 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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val nasti = new NastiIO
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}
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private def opSizeToXSize(ops: UInt) = MuxLookup(ops, UInt("b111"), Seq(
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MT_B -> UInt(0),
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MT_BU -> UInt(0),
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MT_H -> UInt(1),
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MT_HU -> UInt(1),
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MT_W -> UInt(2),
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MT_WU -> UInt(2),
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MT_D -> UInt(3),
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MT_Q -> UInt(log2Up(tlDataBytes))))
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val dataBits = tlDataBits*tlDataBeats
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require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction
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require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
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@ -155,7 +145,7 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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id = get_id_mapper.io.req.out_id,
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addr = io.tl.acquire.bits.full_addr(),
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size = Mux(is_subblock,
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opSizeToXSize(io.tl.acquire.bits.op_size()),
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io.tl.acquire.bits.op_size(),
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UInt(log2Ceil(tlDataBytes))),
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len = Mux(is_subblock, UInt(0), UInt(tlDataBeats - 1)))
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@ -276,13 +266,6 @@ class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p)
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def nasti_addr_byte(chan: NastiAddressChannel): UInt =
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chan.addr(tlByteAddrBits - 1, 0)
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def nasti_operand_size(chan: NastiAddressChannel): UInt =
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MuxLookup(chan.size, MT_Q, Seq(
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UInt(0) -> MT_BU,
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UInt(1) -> MT_HU,
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UInt(2) -> MT_WU,
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UInt(3) -> MT_D))
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def size_mask(size: UInt): UInt =
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(UInt(1) << (UInt(1) << size)) - UInt(1)
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@ -333,7 +316,7 @@ class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p)
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addr_block = nasti_addr_block(io.nasti.ar.bits),
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addr_beat = nasti_addr_beat(io.nasti.ar.bits),
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addr_byte = nasti_addr_byte(io.nasti.ar.bits),
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operand_size = nasti_operand_size(io.nasti.ar.bits),
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operand_size = io.nasti.ar.bits.size,
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alloc = Bool(false)))
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val put_acquire = Mux(is_multibeat(aw_req),
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@ -91,8 +91,7 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
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addr_block = iacq.addr_block,
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addr_beat = iacq.addr_beat,
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data = iacq.data,
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union = Mux(iacq.isBuiltInType(),
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iacq.union, Cat(MT_Q, M_XRD, Bool(true))))
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union = iacq.union)
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io.in.acquire.ready := acq_helper.fire(io.in.acquire.valid)
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relRoq.io.enq.valid := rel_helper.fire(rel_roq_ready, rel_roq_enq)
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@ -418,16 +417,7 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
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assert(!io.in.acquire.valid || !smallput || PopCount(beat_sel) <= UInt(1),
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"Can't perform Put wider than outer width")
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val read_size_ok = MuxLookup(iacq.op_size(), Bool(false), Seq(
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MT_B -> Bool(true),
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MT_BU -> Bool(true),
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MT_H -> Bool(outerDataBits >= 16),
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MT_HU -> Bool(outerDataBits >= 16),
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MT_W -> Bool(outerDataBits >= 32),
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MT_WU -> Bool(outerDataBits >= 32),
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MT_D -> Bool(outerDataBits >= 64),
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MT_Q -> Bool(false)))
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val read_size_ok = iacq.op_size() <= UInt(log2Ceil(outerDataBits / 8))
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assert(!io.in.acquire.valid || !smallget || read_size_ok,
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"Can't perform Get wider than outer width")
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@ -59,8 +59,7 @@ class NastiROM(contents: Seq[Byte])(implicit p: Parameters) extends Module {
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val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
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UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)
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}
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val rdata_word = rom(if (rows == 1) UInt(0) else ar.bits.addr(log2Up(contents.size)-1,log2Up(byteWidth)))
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val rdata = new LoadGen(Cat(UInt(1), ar.bits.size), ar.bits.addr, rdata_word, Bool(false), byteWidth).data
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val rdata = rom(if (rows == 1) UInt(0) else ar.bits.addr(log2Up(contents.size)-1,log2Up(byteWidth)))
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io.r <> ar
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io.r.bits := NastiReadDataChannel(ar.bits.id, rdata)
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@ -72,7 +72,7 @@ trait HasTileLinkParameters {
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val tlBeatAddrBits = log2Up(tlDataBeats)
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val tlByteAddrBits = log2Up(tlWriteMaskBits)
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val tlMemoryOpcodeBits = M_SZ
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val tlMemoryOperandSizeBits = MT_SZ
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val tlMemoryOperandSizeBits = log2Ceil(log2Ceil(tlWriteMaskBits) + 1)
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val tlAcquireTypeBits = max(log2Up(Acquire.nBuiltInTypes),
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tlCoh.acquireTypeWidth)
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val tlAcquireUnionBits = max(tlWriteMaskBits,
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@ -380,10 +380,11 @@ object Acquire {
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val tlExternal = p(TLKey(p(TLId)))
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val tlWriteMaskBits = tlExternal.writeMaskBits
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val tlByteAddrBits = log2Up(tlWriteMaskBits)
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val tlMemoryOperandSizeBits = log2Ceil(log2Ceil(tlWriteMaskBits) + 1)
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// These had better be the right size when we cat them together!
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val my_addr_byte = (UInt(0, tlByteAddrBits) | addr_byte)(tlByteAddrBits-1, 0)
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val my_operand_size = (UInt(0, MT_SZ) | operand_size)(MT_SZ-1, 0)
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val my_operand_size = (UInt(0, tlMemoryOperandSizeBits) | operand_size)(tlMemoryOperandSizeBits-1, 0)
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val my_opcode = (UInt(0, M_SZ) | opcode)(M_SZ-1, 0)
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val my_wmask = (UInt(0, tlWriteMaskBits) | wmask)(tlWriteMaskBits-1, 0)
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@ -436,7 +437,7 @@ object BuiltInAcquireBuilder {
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0),
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addr_byte: UInt = UInt(0),
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operand_size: UInt = MT_Q,
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operand_size: UInt = UInt(0),
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opcode: UInt = UInt(0),
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wmask: UInt = UInt(0),
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alloc: Bool = Bool(true))
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@ -22,13 +22,11 @@ class GetMultiWidthDriver(implicit p: Parameters) extends Driver()(p) {
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val s_start :: s_send :: s_recv :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val size = Reg(UInt(width = MT_SZ))
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val ref = Reg(UInt(width = 64))
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val bytemask = MuxLookup(size, UInt(0), Seq(
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MT_D -> UInt("hff"),
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MT_W -> UInt("h0f"),
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MT_H -> UInt("h03"),
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MT_B -> UInt("h01")))
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val w = 64
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val initialSize = UInt(log2Ceil(w/8))
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val size = Reg(UInt(width = log2Ceil(log2Ceil(w/8)+1)))
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val ref = Reg(UInt(width = w))
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val bytemask = (UInt(1) << (UInt(1) << size)) - UInt(1)
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val bitmask = FillInterleaved(8, bytemask)
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io.mem.acquire.valid := (state === s_send)
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@ -42,20 +40,20 @@ class GetMultiWidthDriver(implicit p: Parameters) extends Driver()(p) {
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io.mem.grant.ready := (state === s_recv)
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when (state === s_start && io.start) {
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size := MT_D
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size := initialSize
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state := s_send
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}
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when (io.mem.acquire.fire()) { state := s_recv }
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when (io.mem.grant.fire()) {
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when (size === MT_D) { ref := io.mem.grant.bits.data }
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when (size === initialSize) { ref := io.mem.grant.bits.data }
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size := size - UInt(1)
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state := Mux(size === MT_B, s_done, s_send)
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state := Mux(size === UInt(0), s_done, s_send)
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}
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io.finished := state === s_done
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assert(!io.mem.grant.valid || size === MT_D ||
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assert(!io.mem.grant.valid || size === initialSize ||
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(io.mem.grant.bits.data & bitmask) === (ref & bitmask),
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"GetMultiWidth: smaller get does not match larger get")
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}
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@ -325,7 +323,7 @@ class PutAtomicDriver(implicit p: Parameters) extends Driver()(p) {
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addr_beat = UInt(0),
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addr_byte = UInt(2),
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atomic_opcode = M_XA_ADD,
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operand_size = MT_H,
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operand_size = UInt(log2Ceil(16 / 8)),
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data = UInt(3 << 16))
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val get_acquire = Get(
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@ -34,9 +34,8 @@ class StoreGenAligned(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) extends St
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override def genData(i: Int) = dat
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}
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class LoadGen(typ: UInt, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
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private val t = new StoreGen(typ, addr, dat, maxSize)
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private val signed = typ.asSInt >= SInt(0)
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class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
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private val size = new StoreGen(typ, addr, dat, maxSize).size
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private def genData(logMinSize: Int): UInt = {
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var res = dat
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@ -45,7 +44,7 @@ class LoadGen(typ: UInt, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
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val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0))
|
||||
val doZero = Bool(i == 0) && zero
|
||||
val zeroed = Mux(doZero, UInt(0), shifted)
|
||||
res = Cat(Mux(t.size === UInt(i) || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)
|
||||
res = Cat(Mux(size === UInt(i) || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)
|
||||
}
|
||||
res
|
||||
}
|
||||
@ -61,7 +60,7 @@ class AMOALU(rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Modu
|
||||
val io = new Bundle {
|
||||
val addr = Bits(INPUT, blockOffBits)
|
||||
val cmd = Bits(INPUT, M_SZ)
|
||||
val typ = Bits(INPUT, MT_SZ)
|
||||
val typ = Bits(INPUT, log2Ceil(log2Ceil(operandBits/8) + 1))
|
||||
val lhs = Bits(INPUT, operandBits)
|
||||
val rhs = Bits(INPUT, operandBits)
|
||||
val out = Bits(OUTPUT, operandBits)
|
||||
@ -75,8 +74,6 @@ class AMOALU(rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Modu
|
||||
val sgned = io.cmd === M_XA_MIN || io.cmd === M_XA_MAX
|
||||
val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
|
||||
val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
|
||||
val word = io.typ === MT_W || io.typ === MT_WU || // Logic minimization:
|
||||
io.typ === MT_B || io.typ === MT_BU
|
||||
|
||||
val adder_out =
|
||||
if (operandBits == 32) io.lhs + rhs
|
||||
@ -88,6 +85,7 @@ class AMOALU(rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Modu
|
||||
val less =
|
||||
if (operandBits == 32) Mux(io.lhs(31) === rhs(31), io.lhs < rhs, Mux(sgned, io.lhs(31), io.rhs(31)))
|
||||
else {
|
||||
val word = !io.typ(0)
|
||||
val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))
|
||||
val cmp_rhs = Mux(word && !io.addr(2), rhs(31), rhs(63))
|
||||
val lt_lo = io.lhs(31,0) < rhs(31,0)
|
||||
|
Loading…
Reference in New Issue
Block a user