From 458520c8f6141b156b630d1533403c25a0617177 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 9 Aug 2016 14:39:06 -0700 Subject: [PATCH] Use a generic UInt for TileLink op sizes, rather than MT_xx enum --- groundtest/src/main/scala/Comparator.scala | 2 +- groundtest/src/main/scala/Generator.scala | 4 ++-- groundtest/src/main/scala/Regression.scala | 10 ++++----- groundtest/src/main/scala/TraceGen.scala | 2 +- riscv-tools | 2 +- rocket/src/main/scala/consts.scala | 12 ++++++++++ rocket/src/main/scala/dcache.scala | 2 +- rocket/src/main/scala/fpu.scala | 2 +- rocket/src/main/scala/nbdcache.scala | 4 ++-- uncore/src/main/scala/Consts.scala | 11 ---------- uncore/src/main/scala/converters/Nasti.scala | 21 ++---------------- .../src/main/scala/converters/Tilelink.scala | 14 ++---------- uncore/src/main/scala/devices/Rom.scala | 3 +-- .../src/main/scala/tilelink/Definitions.scala | 7 +++--- uncore/src/main/scala/unittests/Drivers.scala | 22 +++++++++---------- uncore/src/main/scala/util/AmoAlu.scala | 12 +++++----- 16 files changed, 50 insertions(+), 80 deletions(-) diff --git a/groundtest/src/main/scala/Comparator.scala b/groundtest/src/main/scala/Comparator.scala index 8dc70d5a..e07b5861 100644 --- a/groundtest/src/main/scala/Comparator.scala +++ b/groundtest/src/main/scala/Comparator.scala @@ -82,7 +82,7 @@ class ComparatorSource(implicit val p: Parameters) extends Module val raw_operand_size = NoiseMaker(2, inc) | UInt(0, M_SZ) val max_operand_size = UInt(log2Up(tlDataBytes)) val get_operand_size = Mux(raw_operand_size > max_operand_size, max_operand_size, raw_operand_size) - val atomic_operand_size = Mux(NoiseMaker(1, inc)(0), MT_W, MT_D) + val atomic_operand_size = UInt(2) + NoiseMaker(1, inc) // word or dword // Generate random, but valid addr_bytes val raw_addr_byte = NoiseMaker(tlByteAddrBits, inc) diff --git a/groundtest/src/main/scala/Generator.scala b/groundtest/src/main/scala/Generator.scala index be13b9dd..db839a16 100644 --- a/groundtest/src/main/scala/Generator.scala +++ b/groundtest/src/main/scala/Generator.scala @@ -26,8 +26,8 @@ trait HasGeneratorParameters extends HasGroundTestParameters { val genWordBits = 32 val genWordBytes = genWordBits / 8 - val wordOffset = log2Up(genWordBytes) - val wordSize = MT_WU + val wordOffset = log2Ceil(genWordBytes) + val wordSize = UInt(log2Ceil(genWordBytes)) require(startAddress % BigInt(genWordBytes) == 0) } diff --git a/groundtest/src/main/scala/Regression.scala b/groundtest/src/main/scala/Regression.scala index d4aa41ce..cc347ad6 100644 --- a/groundtest/src/main/scala/Regression.scala +++ b/groundtest/src/main/scala/Regression.scala @@ -25,7 +25,7 @@ abstract class Regression(implicit val p: Parameters) def disableCache() { io.cache.req.valid := Bool(false) io.cache.req.bits.addr := UInt(memStart) - io.cache.req.bits.typ := MT_D + io.cache.req.bits.typ := UInt(0) io.cache.req.bits.cmd := M_XRD io.cache.req.bits.tag := UInt(0) io.cache.req.bits.data := Bits(0) @@ -71,7 +71,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()( io.cache.req.valid := !get_sent && started io.cache.req.bits.addr := UInt(addrMap("io:int:bootrom").start) - io.cache.req.bits.typ := MT_W + io.cache.req.bits.typ := UInt(log2Ceil(32 / 8)) io.cache.req.bits.cmd := M_XRD io.cache.req.bits.tag := UInt(0) io.cache.invalidate_lr := Bool(false) @@ -493,7 +493,7 @@ class ReleaseRegression(implicit p: Parameters) extends Regression()(p) { io.cache.req.valid := sending && (state === s_write || state === s_read) io.cache.req.bits.addr := Cat(addr_blocks(req_idx), UInt(0, blockOffset)) - io.cache.req.bits.typ := MT_D + io.cache.req.bits.typ := UInt(log2Ceil(64 / 8)) io.cache.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD) io.cache.req.bits.tag := UInt(0) io.cache.req.bits.data := data(req_idx) @@ -624,7 +624,7 @@ class MergedPutRegression(implicit p: Parameters) extends Regression()(p) io.cache.req.valid := (state === s_cache_req) io.cache.req.bits.cmd := M_XWR - io.cache.req.bits.typ := MT_D + io.cache.req.bits.typ := UInt(log2Ceil(64 / 8)) io.cache.req.bits.addr := UInt(memStart) io.cache.req.bits.data := UInt(1) io.cache.req.bits.tag := UInt(0) @@ -718,7 +718,7 @@ class RegressionTest(implicit p: Parameters) extends GroundTest()(p) { io.mem.head.grant.ready := Bool(false) io.cache.head.req.valid := Bool(false) io.cache.head.req.bits.addr := UInt(0) - io.cache.head.req.bits.typ := MT_D + io.cache.head.req.bits.typ := UInt(log2Ceil(64 / 8)) io.cache.head.req.bits.cmd := M_XRD io.cache.head.req.bits.tag := UInt(0) io.cache.head.req.bits.phys := Bool(true) diff --git a/groundtest/src/main/scala/TraceGen.scala b/groundtest/src/main/scala/TraceGen.scala index 1eee217b..5070f48f 100644 --- a/groundtest/src/main/scala/TraceGen.scala +++ b/groundtest/src/main/scala/TraceGen.scala @@ -481,7 +481,7 @@ class TraceGenerator(id: Int) io.mem.req.valid := reqValid io.mem.req.bits.addr := reqAddr io.mem.req.bits.data := reqData - io.mem.req.bits.typ := MT_D + io.mem.req.bits.typ := UInt(log2Ceil(numBytesInWord)) io.mem.req.bits.cmd := reqCmd io.mem.req.bits.tag := reqTag diff --git a/riscv-tools b/riscv-tools index 65da94f8..d34419ff 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 65da94f84a2ba5a61a8bcf3ebdd8ca57f6d899ca +Subproject commit d34419ff39072d999371641da520cdce687fd21c diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index f8536da8..421f9f47 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -7,6 +7,18 @@ import Chisel._ import scala.math._ trait ScalarOpConstants { + val MT_SZ = 3 + val MT_X = BitPat("b???") + val MT_B = UInt("b000") + val MT_H = UInt("b001") + val MT_W = UInt("b010") + val MT_D = UInt("b011") + val MT_BU = UInt("b100") + val MT_HU = UInt("b101") + val MT_WU = UInt("b110") + def mtSize(mt: UInt) = mt(MT_SZ-2, 0) + def mtSigned(mt: UInt) = !mt(MT_SZ-1) + val SZ_BR = 3 val BR_X = BitPat("b???") val BR_EQ = UInt(0, 3) diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala index 81326957..352e8140 100644 --- a/rocket/src/main/scala/dcache.scala +++ b/rocket/src/main/scala/dcache.scala @@ -397,7 +397,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) { // load data subword mux/sign extension val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_word = s2_data >> Cat(s2_word_idx, UInt(0, log2Up(coreDataBits))) - val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc, wordBytes) + val loadgen = new LoadGen(s2_req.typ, mtSigned(s2_req.typ), s2_req.addr, s2_data_word, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data | s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.store_data := pstore1_data diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index bb22cf03..5c4a27a8 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -443,7 +443,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) { // load response val load_wb = Reg(next=io.dmem_resp_val) - val load_wb_single = RegEnable(io.dmem_resp_type === MT_W || io.dmem_resp_type === MT_WU, io.dmem_resp_val) + val load_wb_single = RegEnable(!io.dmem_resp_type(0), io.dmem_resp_val) val load_wb_data = RegEnable(io.dmem_resp_data, io.dmem_resp_val) val load_wb_tag = RegEnable(io.dmem_resp_tag, io.dmem_resp_val) val rec_s = hardfloat.recFNFromFN(8, 24, load_wb_data) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 0c281438..f5e22fc2 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -187,7 +187,7 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) { fq.io.deq.ready := io.finish.ready && (state === s_finish) val storegen = new StoreGen(req.typ, req.addr, req.data, wordBytes) - val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc, wordBytes) + val loadgen = new LoadGen(req.typ, mtSigned(req.typ), req.addr, grant_word, req_cmd_sc, wordBytes) val beat_mask = (storegen.mask << Cat(beatOffset(req.addr), UInt(0, wordOffBits))) val beat_data = Fill(beatWords, storegen.data) @@ -1062,7 +1062,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) { // load data subword mux/sign extension val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(coreDataBits))) val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass) - val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc, wordBytes) + val loadgen = new LoadGen(s2_req.typ, mtSigned(s2_req.typ), s2_req.addr, s2_data_word, s2_sc, wordBytes) amoalu.io.addr := s2_req.addr amoalu.io.cmd := s2_req.cmd diff --git a/uncore/src/main/scala/Consts.scala b/uncore/src/main/scala/Consts.scala index a4a4e93b..a49d69a5 100644 --- a/uncore/src/main/scala/Consts.scala +++ b/uncore/src/main/scala/Consts.scala @@ -7,17 +7,6 @@ import Chisel._ object MemoryOpConstants extends MemoryOpConstants trait MemoryOpConstants { - val MT_SZ = 3 - val MT_X = BitPat("b???") - val MT_B = UInt("b000") - val MT_H = UInt("b001") - val MT_W = UInt("b010") - val MT_D = UInt("b011") - val MT_BU = UInt("b100") - val MT_HU = UInt("b101") - val MT_WU = UInt("b110") - val MT_Q = UInt("b111") - val NUM_XA_OPS = 9 val M_SZ = 5 val M_X = BitPat("b?????"); diff --git a/uncore/src/main/scala/converters/Nasti.scala b/uncore/src/main/scala/converters/Nasti.scala index c56aab4c..aed5f6bc 100644 --- a/uncore/src/main/scala/converters/Nasti.scala +++ b/uncore/src/main/scala/converters/Nasti.scala @@ -73,16 +73,6 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p) val nasti = new NastiIO } - private def opSizeToXSize(ops: UInt) = MuxLookup(ops, UInt("b111"), Seq( - MT_B -> UInt(0), - MT_BU -> UInt(0), - MT_H -> UInt(1), - MT_HU -> UInt(1), - MT_W -> UInt(2), - MT_WU -> UInt(2), - MT_D -> UInt(3), - MT_Q -> UInt(log2Up(tlDataBytes)))) - val dataBits = tlDataBits*tlDataBeats require(tlDataBits == nastiXDataBits, "Data sizes between LLC and MC don't agree") // TODO: remove this restriction require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats") @@ -155,7 +145,7 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p) id = get_id_mapper.io.req.out_id, addr = io.tl.acquire.bits.full_addr(), size = Mux(is_subblock, - opSizeToXSize(io.tl.acquire.bits.op_size()), + io.tl.acquire.bits.op_size(), UInt(log2Ceil(tlDataBytes))), len = Mux(is_subblock, UInt(0), UInt(tlDataBeats - 1))) @@ -276,13 +266,6 @@ class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p) def nasti_addr_byte(chan: NastiAddressChannel): UInt = chan.addr(tlByteAddrBits - 1, 0) - def nasti_operand_size(chan: NastiAddressChannel): UInt = - MuxLookup(chan.size, MT_Q, Seq( - UInt(0) -> MT_BU, - UInt(1) -> MT_HU, - UInt(2) -> MT_WU, - UInt(3) -> MT_D)) - def size_mask(size: UInt): UInt = (UInt(1) << (UInt(1) << size)) - UInt(1) @@ -333,7 +316,7 @@ class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p) addr_block = nasti_addr_block(io.nasti.ar.bits), addr_beat = nasti_addr_beat(io.nasti.ar.bits), addr_byte = nasti_addr_byte(io.nasti.ar.bits), - operand_size = nasti_operand_size(io.nasti.ar.bits), + operand_size = io.nasti.ar.bits.size, alloc = Bool(false))) val put_acquire = Mux(is_multibeat(aw_req), diff --git a/uncore/src/main/scala/converters/Tilelink.scala b/uncore/src/main/scala/converters/Tilelink.scala index 678bb72b..99a493e2 100644 --- a/uncore/src/main/scala/converters/Tilelink.scala +++ b/uncore/src/main/scala/converters/Tilelink.scala @@ -91,8 +91,7 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) { addr_block = iacq.addr_block, addr_beat = iacq.addr_beat, data = iacq.data, - union = Mux(iacq.isBuiltInType(), - iacq.union, Cat(MT_Q, M_XRD, Bool(true)))) + union = iacq.union) io.in.acquire.ready := acq_helper.fire(io.in.acquire.valid) relRoq.io.enq.valid := rel_helper.fire(rel_roq_ready, rel_roq_enq) @@ -418,16 +417,7 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String) assert(!io.in.acquire.valid || !smallput || PopCount(beat_sel) <= UInt(1), "Can't perform Put wider than outer width") - val read_size_ok = MuxLookup(iacq.op_size(), Bool(false), Seq( - MT_B -> Bool(true), - MT_BU -> Bool(true), - MT_H -> Bool(outerDataBits >= 16), - MT_HU -> Bool(outerDataBits >= 16), - MT_W -> Bool(outerDataBits >= 32), - MT_WU -> Bool(outerDataBits >= 32), - MT_D -> Bool(outerDataBits >= 64), - MT_Q -> Bool(false))) - + val read_size_ok = iacq.op_size() <= UInt(log2Ceil(outerDataBits / 8)) assert(!io.in.acquire.valid || !smallget || read_size_ok, "Can't perform Get wider than outer width") diff --git a/uncore/src/main/scala/devices/Rom.scala b/uncore/src/main/scala/devices/Rom.scala index 0fd9dd3e..f2210d03 100644 --- a/uncore/src/main/scala/devices/Rom.scala +++ b/uncore/src/main/scala/devices/Rom.scala @@ -59,8 +59,7 @@ class NastiROM(contents: Seq[Byte])(implicit p: Parameters) extends Module { val slice = contents.slice(i*byteWidth, (i+1)*byteWidth) UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8) } - val rdata_word = rom(if (rows == 1) UInt(0) else ar.bits.addr(log2Up(contents.size)-1,log2Up(byteWidth))) - val rdata = new LoadGen(Cat(UInt(1), ar.bits.size), ar.bits.addr, rdata_word, Bool(false), byteWidth).data + val rdata = rom(if (rows == 1) UInt(0) else ar.bits.addr(log2Up(contents.size)-1,log2Up(byteWidth))) io.r <> ar io.r.bits := NastiReadDataChannel(ar.bits.id, rdata) diff --git a/uncore/src/main/scala/tilelink/Definitions.scala b/uncore/src/main/scala/tilelink/Definitions.scala index 0884fd5b..ff3a6067 100644 --- a/uncore/src/main/scala/tilelink/Definitions.scala +++ b/uncore/src/main/scala/tilelink/Definitions.scala @@ -72,7 +72,7 @@ trait HasTileLinkParameters { val tlBeatAddrBits = log2Up(tlDataBeats) val tlByteAddrBits = log2Up(tlWriteMaskBits) val tlMemoryOpcodeBits = M_SZ - val tlMemoryOperandSizeBits = MT_SZ + val tlMemoryOperandSizeBits = log2Ceil(log2Ceil(tlWriteMaskBits) + 1) val tlAcquireTypeBits = max(log2Up(Acquire.nBuiltInTypes), tlCoh.acquireTypeWidth) val tlAcquireUnionBits = max(tlWriteMaskBits, @@ -380,10 +380,11 @@ object Acquire { val tlExternal = p(TLKey(p(TLId))) val tlWriteMaskBits = tlExternal.writeMaskBits val tlByteAddrBits = log2Up(tlWriteMaskBits) + val tlMemoryOperandSizeBits = log2Ceil(log2Ceil(tlWriteMaskBits) + 1) // These had better be the right size when we cat them together! val my_addr_byte = (UInt(0, tlByteAddrBits) | addr_byte)(tlByteAddrBits-1, 0) - val my_operand_size = (UInt(0, MT_SZ) | operand_size)(MT_SZ-1, 0) + val my_operand_size = (UInt(0, tlMemoryOperandSizeBits) | operand_size)(tlMemoryOperandSizeBits-1, 0) val my_opcode = (UInt(0, M_SZ) | opcode)(M_SZ-1, 0) val my_wmask = (UInt(0, tlWriteMaskBits) | wmask)(tlWriteMaskBits-1, 0) @@ -436,7 +437,7 @@ object BuiltInAcquireBuilder { addr_beat: UInt = UInt(0), data: UInt = UInt(0), addr_byte: UInt = UInt(0), - operand_size: UInt = MT_Q, + operand_size: UInt = UInt(0), opcode: UInt = UInt(0), wmask: UInt = UInt(0), alloc: Bool = Bool(true)) diff --git a/uncore/src/main/scala/unittests/Drivers.scala b/uncore/src/main/scala/unittests/Drivers.scala index 0665534f..b23b9e95 100644 --- a/uncore/src/main/scala/unittests/Drivers.scala +++ b/uncore/src/main/scala/unittests/Drivers.scala @@ -22,13 +22,11 @@ class GetMultiWidthDriver(implicit p: Parameters) extends Driver()(p) { val s_start :: s_send :: s_recv :: s_done :: Nil = Enum(Bits(), 4) val state = Reg(init = s_start) - val size = Reg(UInt(width = MT_SZ)) - val ref = Reg(UInt(width = 64)) - val bytemask = MuxLookup(size, UInt(0), Seq( - MT_D -> UInt("hff"), - MT_W -> UInt("h0f"), - MT_H -> UInt("h03"), - MT_B -> UInt("h01"))) + val w = 64 + val initialSize = UInt(log2Ceil(w/8)) + val size = Reg(UInt(width = log2Ceil(log2Ceil(w/8)+1))) + val ref = Reg(UInt(width = w)) + val bytemask = (UInt(1) << (UInt(1) << size)) - UInt(1) val bitmask = FillInterleaved(8, bytemask) io.mem.acquire.valid := (state === s_send) @@ -42,20 +40,20 @@ class GetMultiWidthDriver(implicit p: Parameters) extends Driver()(p) { io.mem.grant.ready := (state === s_recv) when (state === s_start && io.start) { - size := MT_D + size := initialSize state := s_send } when (io.mem.acquire.fire()) { state := s_recv } when (io.mem.grant.fire()) { - when (size === MT_D) { ref := io.mem.grant.bits.data } + when (size === initialSize) { ref := io.mem.grant.bits.data } size := size - UInt(1) - state := Mux(size === MT_B, s_done, s_send) + state := Mux(size === UInt(0), s_done, s_send) } io.finished := state === s_done - assert(!io.mem.grant.valid || size === MT_D || + assert(!io.mem.grant.valid || size === initialSize || (io.mem.grant.bits.data & bitmask) === (ref & bitmask), "GetMultiWidth: smaller get does not match larger get") } @@ -325,7 +323,7 @@ class PutAtomicDriver(implicit p: Parameters) extends Driver()(p) { addr_beat = UInt(0), addr_byte = UInt(2), atomic_opcode = M_XA_ADD, - operand_size = MT_H, + operand_size = UInt(log2Ceil(16 / 8)), data = UInt(3 << 16)) val get_acquire = Get( diff --git a/uncore/src/main/scala/util/AmoAlu.scala b/uncore/src/main/scala/util/AmoAlu.scala index efc538b7..965ddad1 100644 --- a/uncore/src/main/scala/util/AmoAlu.scala +++ b/uncore/src/main/scala/util/AmoAlu.scala @@ -34,9 +34,8 @@ class StoreGenAligned(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) extends St override def genData(i: Int) = dat } -class LoadGen(typ: UInt, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { - private val t = new StoreGen(typ, addr, dat, maxSize) - private val signed = typ.asSInt >= SInt(0) +class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { + private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat @@ -45,7 +44,7 @@ class LoadGen(typ: UInt, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = Bool(i == 0) && zero val zeroed = Mux(doZero, UInt(0), shifted) - res = Cat(Mux(t.size === UInt(i) || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) + res = Cat(Mux(size === UInt(i) || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } @@ -61,7 +60,7 @@ class AMOALU(rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Modu val io = new Bundle { val addr = Bits(INPUT, blockOffBits) val cmd = Bits(INPUT, M_SZ) - val typ = Bits(INPUT, MT_SZ) + val typ = Bits(INPUT, log2Ceil(log2Ceil(operandBits/8) + 1)) val lhs = Bits(INPUT, operandBits) val rhs = Bits(INPUT, operandBits) val out = Bits(OUTPUT, operandBits) @@ -75,8 +74,6 @@ class AMOALU(rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Modu val sgned = io.cmd === M_XA_MIN || io.cmd === M_XA_MAX val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU - val word = io.typ === MT_W || io.typ === MT_WU || // Logic minimization: - io.typ === MT_B || io.typ === MT_BU val adder_out = if (operandBits == 32) io.lhs + rhs @@ -88,6 +85,7 @@ class AMOALU(rhsIsAligned: Boolean = false)(implicit p: Parameters) extends Modu val less = if (operandBits == 32) Mux(io.lhs(31) === rhs(31), io.lhs < rhs, Mux(sgned, io.lhs(31), io.rhs(31))) else { + val word = !io.typ(0) val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63)) val cmp_rhs = Mux(word && !io.addr(2), rhs(31), rhs(63)) val lt_lo = io.lhs(31,0) < rhs(31,0)