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Use a generic UInt for TileLink op sizes, rather than MT_xx enum

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This commit is contained in:
Andrew Waterman
2016-08-09 14:39:06 -07:00
parent a857b08c59
commit 458520c8f6
16 changed files with 50 additions and 80 deletions
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7
uncore/src/main/scala/tilelink/Definitions.scala
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@ -72,7 +72,7 @@ trait HasTileLinkParameters {
val tlBeatAddrBits = log2Up(tlDataBeats)
val tlByteAddrBits = log2Up(tlWriteMaskBits)
val tlMemoryOpcodeBits = M_SZ
val tlMemoryOperandSizeBits = MT_SZ
val tlMemoryOperandSizeBits = log2Ceil(log2Ceil(tlWriteMaskBits) + 1)
val tlAcquireTypeBits = max(log2Up(Acquire.nBuiltInTypes),
tlCoh.acquireTypeWidth)
val tlAcquireUnionBits = max(tlWriteMaskBits,
@ -380,10 +380,11 @@ object Acquire {
val tlExternal = p(TLKey(p(TLId)))
val tlWriteMaskBits = tlExternal.writeMaskBits
val tlByteAddrBits = log2Up(tlWriteMaskBits)
val tlMemoryOperandSizeBits = log2Ceil(log2Ceil(tlWriteMaskBits) + 1)
// These had better be the right size when we cat them together!
val my_addr_byte = (UInt(0, tlByteAddrBits) | addr_byte)(tlByteAddrBits-1, 0)
val my_operand_size = (UInt(0, MT_SZ) | operand_size)(MT_SZ-1, 0)
val my_operand_size = (UInt(0, tlMemoryOperandSizeBits) | operand_size)(tlMemoryOperandSizeBits-1, 0)
val my_opcode = (UInt(0, M_SZ) | opcode)(M_SZ-1, 0)
val my_wmask = (UInt(0, tlWriteMaskBits) | wmask)(tlWriteMaskBits-1, 0)
@ -436,7 +437,7 @@ object BuiltInAcquireBuilder {
addr_beat: UInt = UInt(0),
data: UInt = UInt(0),
addr_byte: UInt = UInt(0),
operand_size: UInt = MT_Q,
operand_size: UInt = UInt(0),
opcode: UInt = UInt(0),
wmask: UInt = UInt(0),
alloc: Bool = Bool(true))