riscv/rocket-chip
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Use a generic UInt for TileLink op sizes, rather than MT_xx enum

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This commit is contained in:
Andrew Waterman
2016-08-09 14:39:06 -07:00
parent a857b08c59
commit 458520c8f6
16 changed files with 50 additions and 80 deletions
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3
uncore/src/main/scala/devices/Rom.scala
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@ -59,8 +59,7 @@ class NastiROM(contents: Seq[Byte])(implicit p: Parameters) extends Module {
val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)
}
val rdata_word = rom(if (rows == 1) UInt(0) else ar.bits.addr(log2Up(contents.size)-1,log2Up(byteWidth)))
val rdata = new LoadGen(Cat(UInt(1), ar.bits.size), ar.bits.addr, rdata_word, Bool(false), byteWidth).data
val rdata = rom(if (rows == 1) UInt(0) else ar.bits.addr(log2Up(contents.size)-1,log2Up(byteWidth)))
io.r <> ar
io.r.bits := NastiReadDataChannel(ar.bits.id, rdata)