Use a generic UInt for TileLink op sizes, rather than MT_xx enum

groundtest/src/main/scala/Comparator.scala

@@ -82,7 +82,7 @@ class ComparatorSource(implicit val p: Parameters) extends Module
   val raw_operand_size = NoiseMaker(2, inc) | UInt(0, M_SZ)
   val max_operand_size = UInt(log2Up(tlDataBytes))
   val get_operand_size = Mux(raw_operand_size > max_operand_size, max_operand_size, raw_operand_size)
-  val atomic_operand_size = Mux(NoiseMaker(1, inc)(0), MT_W, MT_D)
+  val atomic_operand_size = UInt(2) + NoiseMaker(1, inc) // word or dword
   
   // Generate random, but valid addr_bytes
   val raw_addr_byte = NoiseMaker(tlByteAddrBits, inc)

groundtest/src/main/scala/Generator.scala

@@ -26,8 +26,8 @@ trait HasGeneratorParameters extends HasGroundTestParameters {
 
   val genWordBits = 32
   val genWordBytes = genWordBits / 8
-  val wordOffset = log2Up(genWordBytes)
-  val wordSize = MT_WU
+  val wordOffset = log2Ceil(genWordBytes)
+  val wordSize = UInt(log2Ceil(genWordBytes))
 
   require(startAddress % BigInt(genWordBytes) == 0)
 }

groundtest/src/main/scala/Regression.scala

@@ -25,7 +25,7 @@ abstract class Regression(implicit val p: Parameters)
   def disableCache() {
     io.cache.req.valid := Bool(false)
     io.cache.req.bits.addr := UInt(memStart)
-    io.cache.req.bits.typ  := MT_D
+    io.cache.req.bits.typ  := UInt(0)
     io.cache.req.bits.cmd  := M_XRD
     io.cache.req.bits.tag  := UInt(0)
     io.cache.req.bits.data := Bits(0)
@@ -71,7 +71,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
 
   io.cache.req.valid := !get_sent && started
   io.cache.req.bits.addr := UInt(addrMap("io:int:bootrom").start)
-  io.cache.req.bits.typ := MT_W
+  io.cache.req.bits.typ := UInt(log2Ceil(32 / 8))
   io.cache.req.bits.cmd := M_XRD
   io.cache.req.bits.tag := UInt(0)
   io.cache.invalidate_lr := Bool(false)
@@ -493,7 +493,7 @@ class ReleaseRegression(implicit p: Parameters) extends Regression()(p) {
 
   io.cache.req.valid := sending && (state === s_write || state === s_read)
   io.cache.req.bits.addr := Cat(addr_blocks(req_idx), UInt(0, blockOffset))
-  io.cache.req.bits.typ := MT_D
+  io.cache.req.bits.typ := UInt(log2Ceil(64 / 8))
   io.cache.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
   io.cache.req.bits.tag := UInt(0)
   io.cache.req.bits.data := data(req_idx)
@@ -624,7 +624,7 @@ class MergedPutRegression(implicit p: Parameters) extends Regression()(p)
 
   io.cache.req.valid := (state === s_cache_req)
   io.cache.req.bits.cmd := M_XWR
-  io.cache.req.bits.typ := MT_D
+  io.cache.req.bits.typ := UInt(log2Ceil(64 / 8))
   io.cache.req.bits.addr := UInt(memStart)
   io.cache.req.bits.data := UInt(1)
   io.cache.req.bits.tag := UInt(0)
@@ -718,7 +718,7 @@ class RegressionTest(implicit p: Parameters) extends GroundTest()(p) {
   io.mem.head.grant.ready := Bool(false)
   io.cache.head.req.valid := Bool(false)
   io.cache.head.req.bits.addr := UInt(0)
-  io.cache.head.req.bits.typ := MT_D
+  io.cache.head.req.bits.typ := UInt(log2Ceil(64 / 8))
   io.cache.head.req.bits.cmd := M_XRD
   io.cache.head.req.bits.tag := UInt(0)
   io.cache.head.req.bits.phys := Bool(true)

groundtest/src/main/scala/TraceGen.scala

@@ -481,7 +481,7 @@ class TraceGenerator(id: Int)
   io.mem.req.valid     := reqValid
   io.mem.req.bits.addr := reqAddr
   io.mem.req.bits.data := reqData
-  io.mem.req.bits.typ  := MT_D
+  io.mem.req.bits.typ  := UInt(log2Ceil(numBytesInWord))
   io.mem.req.bits.cmd  := reqCmd
   io.mem.req.bits.tag  := reqTag