riscv/rocket-chip
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rocket: use diplomatic interrupts

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This makes it possible for the PLIC to work with heterogenous cores.
This commit is contained in:
Wesley W. Terpstra
2017-03-02 13:37:25 -08:00
parent d3c5318714
commit 4535de2669
6 changed files with 52 additions and 58 deletions
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5
src/main/scala/uncore/devices/Plic.scala
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@ -53,9 +53,8 @@ object PLICConsts
}
/** Platform-Level Interrupt Controller */
class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parameters) extends LazyModule
class TLPLIC(maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parameters) extends LazyModule
{
val contextsPerHart = if (supervisor) 2 else 1
require (maxPriorities >= 0)
// plic0 => max devices 1023
@ -81,7 +80,7 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
val intnode = IntNexusNode(
numSourcePorts = 0 to 1024,
numSinkPorts = 0 to 1024,
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(contextsPerHart, Seq(Resource(device, "int"))))) },
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
/* Negotiated sizes */