riscv/rocket-chip
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Avoid data corruption under correctable tag error during flush (#1130)

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This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
This commit is contained in:
Andrew Waterman 2017-11-29 09:42:00 -08:00 committed by Henry Cook
parent 9d489c6dcd
commit 44eb4d12b5
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/rocket/DCache.scala
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@ -242,8 +242,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
} }
val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_way = RegEnable(s1_hit_way, s1_probe)
val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe)
val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked || s1_flush_valid)
val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked || s1_flush_valid)
val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked)
val s2_store_merge = Wire(Bool()) val s2_store_merge = Wire(Bool())
val s2_hit_valid = s2_hit_state.isValid() val s2_hit_valid = s2_hit_state.isValid()