riscv/rocket-chip
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Use more generic TileLinkWidthAdapter

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This commit is contained in:
Andrew Waterman 2016-05-26 22:24:40 -07:00
parent 10f0e13c25
commit 44a216038f
4 changed files with 5 additions and 10 deletions
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2
junctions

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Subproject commit 9522bc5a2a3e45601a0578f3f7ff1a84979cdf02 Subproject commit b912b7cd1263d7f3b63e6fcb052d9d7493d1b970

2
rocket

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Subproject commit a2c51cfabe3029121b5f8d8136a8137da5e2802f Subproject commit 0fa4b431ccdcf27380a224ba18d2658f3123ddeb

9
src/main/scala/RocketChip.scala
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@ -194,11 +194,8 @@ class Uncore(implicit val p: Parameters) extends Module
val (ioBase, ioAddrMap) = addrHashMap.subMap("io") val (ioBase, ioAddrMap) = addrHashMap.subMap("io")
val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase) val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase)
val mmioNarrower = Module(new TileLinkIONarrower("L2toMMIO", "MMIO_Outermost"))
val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap, ioBase)) val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap, ioBase))
TileLinkWidthAdapter(outmemsys.io.mmio, mmioNetwork.io.in.head)
mmioNarrower.io.in <> outmemsys.io.mmio
mmioNetwork.io.in.head <> mmioNarrower.io.out
val rtc = Module(new RTC(p(NTiles))) val rtc = Module(new RTC(p(NTiles)))
val rtcAddr = ioAddrHashMap("int:rtc") val rtcAddr = ioAddrHashMap("int:rtc")
@ -309,10 +306,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) { for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams)) val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams) unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
narrow.io.in <> unwrap.io.out TileLinkWidthAdapter(unwrap.io.out, icPort)
icPort <> narrow.io.out
} }
for ((nasti, tl) <- io.mem zip mem_ic.io.out) { for ((nasti, tl) <- io.mem zip mem_ic.io.out) {

2
uncore

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Subproject commit e37eea2c33c510c18d1b7f750f45a92dcadb91b1 Subproject commit 040fd49d273cfda0c51d949856ab130417b9f6f2