From 44a216038fda2fb4d65944065f4f2508fcdc33c2 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 26 May 2016 22:24:40 -0700
Subject: [PATCH] Use more generic TileLinkWidthAdapter

---
 junctions                       | 2 +-
 rocket                          | 2 +-
 src/main/scala/RocketChip.scala | 9 ++-------
 uncore                          | 2 +-
 4 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/junctions b/junctions
index 9522bc5a..b912b7cd 160000
--- a/junctions
+++ b/junctions
@@ -1 +1 @@
-Subproject commit 9522bc5a2a3e45601a0578f3f7ff1a84979cdf02
+Subproject commit b912b7cd1263d7f3b63e6fcb052d9d7493d1b970
diff --git a/rocket b/rocket
index a2c51cfa..0fa4b431 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit a2c51cfabe3029121b5f8d8136a8137da5e2802f
+Subproject commit 0fa4b431ccdcf27380a224ba18d2658f3123ddeb
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index e1a5a606..9f079d65 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -194,11 +194,8 @@ class Uncore(implicit val p: Parameters) extends Module
     val (ioBase, ioAddrMap) = addrHashMap.subMap("io")
     val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase)
 
-    val mmioNarrower = Module(new TileLinkIONarrower("L2toMMIO", "MMIO_Outermost"))
     val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap, ioBase))
-
-    mmioNarrower.io.in <> outmemsys.io.mmio
-    mmioNetwork.io.in.head <> mmioNarrower.io.out
+    TileLinkWidthAdapter(outmemsys.io.mmio, mmioNetwork.io.in.head)
 
     val rtc = Module(new RTC(p(NTiles)))
     val rtcAddr = ioAddrHashMap("int:rtc")
@@ -309,10 +306,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
 
   for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
     val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
-    val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
     unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
-    narrow.io.in <> unwrap.io.out
-    icPort <> narrow.io.out
+    TileLinkWidthAdapter(unwrap.io.out, icPort)
   }
 
   for ((nasti, tl) <- io.mem zip mem_ic.io.out) {
diff --git a/uncore b/uncore
index e37eea2c..040fd49d 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit e37eea2c33c510c18d1b7f750f45a92dcadb91b1
+Subproject commit 040fd49d273cfda0c51d949856ab130417b9f6f2