riscv/rocket-chip
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Use more generic TileLinkWidthAdapter

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This commit is contained in:
Andrew Waterman
2016-05-26 22:24:40 -07:00
parent 10f0e13c25
commit 44a216038f
4 changed files with 5 additions and 10 deletions
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9
src/main/scala/RocketChip.scala
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@ -194,11 +194,8 @@ class Uncore(implicit val p: Parameters) extends Module
val (ioBase, ioAddrMap) = addrHashMap.subMap("io")
val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase)
val mmioNarrower = Module(new TileLinkIONarrower("L2toMMIO", "MMIO_Outermost"))
val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap, ioBase))
mmioNarrower.io.in <> outmemsys.io.mmio
mmioNetwork.io.in.head <> mmioNarrower.io.out
TileLinkWidthAdapter(outmemsys.io.mmio, mmioNetwork.io.in.head)
val rtc = Module(new RTC(p(NTiles)))
val rtcAddr = ioAddrHashMap("int:rtc")
@ -309,10 +306,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
narrow.io.in <> unwrap.io.out
icPort <> narrow.io.out
TileLinkWidthAdapter(unwrap.io.out, icPort)
}
for ((nasti, tl) <- io.mem zip mem_ic.io.out) {