jtag: Connect the JTAG DTM side of the synchronizer!
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@ -220,16 +220,16 @@ install_openocd: $(OPENOCD_DIR)/bin/openocd
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# Running a list of tests is not supported.
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JTAG_DTM_TEST ?= SimpleRegisterTest.test_s0
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stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp
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stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug.stamp
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$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
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--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
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--run "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*-debug +vcdplusfile=foo.vpd" \
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--cmd="$(OPENOCD_DIR)/bin/openocd \
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--s $(OPENOCD_DIR)/share/openocd/scripts" \
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--freedom-e300-sim \
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$(JTAG_DTM_TEST)
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date > $@
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stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp
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stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug.stamp
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$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
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--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
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--cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd \
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@ -54,7 +54,7 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
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val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width))
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jtag_dtm.io.jtag <> io.jtag
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jtag_dtm.io.jtag := io.jtag
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val dtm_req = Wire(new DecoupledIO(UInt(width = req_width)))
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val dtm_resp = Wire(new DecoupledIO(UInt(width = resp_width)))
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@ -72,6 +72,9 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
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dtm_resp.valid := io_debug_bus.resp.valid
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dtm_resp.bits := io_debug_bus.resp.bits.asUInt
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io_debug_bus.resp.ready := dtm_resp.ready
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dtm_req := jtag_dtm.io.dtm_req
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jtag_dtm.io.dtm_resp := dtm_resp
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}
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class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox {
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