From 449d689a4ed4ef79eca9147dd9e26f66e3e070b9 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 26 Sep 2016 20:28:26 -0700
Subject: [PATCH] jtag: Connect the JTAG DTM side of the synchronizer!

---
 regression/Makefile                            | 6 +++---
 src/main/scala/rocketchip/DebugTransport.scala | 5 ++++-
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/regression/Makefile b/regression/Makefile
index 32cf5b05..945fb602 100644
--- a/regression/Makefile
+++ b/regression/Makefile
@@ -220,16 +220,16 @@ install_openocd: $(OPENOCD_DIR)/bin/openocd
 # Running a list of tests is not supported.
 JTAG_DTM_TEST ?= SimpleRegisterTest.test_s0
 
-stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp
+stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug.stamp
 	$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
-	--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
+	--run "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*-debug +vcdplusfile=foo.vpd" \
 	--cmd="$(OPENOCD_DIR)/bin/openocd \
 	--s $(OPENOCD_DIR)/share/openocd/scripts" \
 	--freedom-e300-sim \
 	$(JTAG_DTM_TEST)
 	date > $@
 
-stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp
+stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug.stamp
 	$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
 	--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
 	--cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd \
diff --git a/src/main/scala/rocketchip/DebugTransport.scala b/src/main/scala/rocketchip/DebugTransport.scala
index e0d557e2..0305a3ff 100644
--- a/src/main/scala/rocketchip/DebugTransport.scala
+++ b/src/main/scala/rocketchip/DebugTransport.scala
@@ -54,7 +54,7 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
 
   val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width))
 
-  jtag_dtm.io.jtag <> io.jtag
+  jtag_dtm.io.jtag := io.jtag
 
   val dtm_req = Wire(new DecoupledIO(UInt(width = req_width)))
   val dtm_resp = Wire(new DecoupledIO(UInt(width = resp_width)))
@@ -72,6 +72,9 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
   dtm_resp.valid := io_debug_bus.resp.valid
   dtm_resp.bits  := io_debug_bus.resp.bits.asUInt
   io_debug_bus.resp.ready  := dtm_resp.ready
+
+  dtm_req := jtag_dtm.io.dtm_req
+  jtag_dtm.io.dtm_resp := dtm_resp
 }
 
 class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters)  extends BlackBox {